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target/arm: fix TCG leak for fcvt half->double

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When support for the AHP flag was added we inexplicably only freed the
new temps in one of the two legs. Move those tcg_temp_free to the same
level as the allocation to fix that leak.

Backports commit aeab8e5eb220cc5ff84b0b68b9afccc611bf0fcd from qemu
This commit is contained in:
Alex Bennée 2020-03-21 13:14:36 -04:00 committed by Lioncash
parent 7fbc373f59
commit ced8834737
2 changed files with 4 additions and 8 deletions
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4
qemu/target/arm/translate-a64.c
View file

@ -6023,8 +6023,6 @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
TCGv_i32 tcg_rd = tcg_temp_new_i32(tcg_ctx); TCGv_i32 tcg_rd = tcg_temp_new_i32(tcg_ctx);
gen_helper_vfp_fcvt_f16_to_f32(tcg_ctx, tcg_rd, tcg_rn, tcg_fpst, tcg_ahp); gen_helper_vfp_fcvt_f16_to_f32(tcg_ctx, tcg_rd, tcg_rn, tcg_fpst, tcg_ahp);
write_fp_sreg(s, rd, tcg_rd); write_fp_sreg(s, rd, tcg_rd);
tcg_temp_free_ptr(tcg_ctx, tcg_fpst);
tcg_temp_free_i32(tcg_ctx, tcg_ahp);
tcg_temp_free_i32(tcg_ctx, tcg_rd); tcg_temp_free_i32(tcg_ctx, tcg_rd);
} else { } else {
/* Half to double */ /* Half to double */
@ -6034,6 +6032,8 @@ static void handle_fp_fcvt(DisasContext *s, int opcode,
tcg_temp_free_i64(tcg_ctx, tcg_rd); tcg_temp_free_i64(tcg_ctx, tcg_rd);
} }
tcg_temp_free_i32(tcg_ctx, tcg_rn); tcg_temp_free_i32(tcg_ctx, tcg_rn);
tcg_temp_free_ptr(tcg_ctx, tcg_fpst);
tcg_temp_free_i32(tcg_ctx, tcg_ahp);
break; break;
} }
default: default:

8
qemu/target/mips/op_helper.c
View file

@ -2545,17 +2545,13 @@ void helper_ginvt(CPUMIPSState *env, target_ulong arg, uint32_t type)
uint32_t invMsgVPN2 = arg & (TARGET_PAGE_MASK << 1); uint32_t invMsgVPN2 = arg & (TARGET_PAGE_MASK << 1);
uint8_t invMsgR = 0; uint8_t invMsgR = 0;
uint32_t invMsgMMid = env->CP0_MemoryMapID; uint32_t invMsgMMid = env->CP0_MemoryMapID;
CPUState *other_cs = first_cpu;
#ifdef TARGET_MIPS64 #ifdef TARGET_MIPS64
invMsgR = extract64(arg, 62, 2); invMsgR = extract64(arg, 62, 2);
#endif #endif
CPU_FOREACH(other_cs) { global_invalidate_tlb(env, invMsgVPN2, invMsgR, invMsgMMid,
MIPSCPU *other_cpu = MIPS_CPU(other_cs); invAll, invVAMMid, invMMid, invVA);
global_invalidate_tlb(&other_cpu->env, invMsgVPN2, invMsgR, invMsgMMid,
invAll, invVAMMid, invMMid, invVA);
}
} }
/* Specials */ /* Specials */