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https://github.com/yuzu-emu/unicorn.git
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target-m68k: Inline shifts
Also manage word and byte operands and fix the computation of overflow in the case of M68000 arithmetic shifts. Backports commit 367790cce8e14131426f5190dfd7d1bdbf656e4d from qemu
This commit is contained in:
Richard Henderson
Lioncash
parent
0c00b036be
commit
cf9424d60d
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@ -198,58 +198,6 @@ void HELPER(set_sr)(CPUM68KState *env, uint32_t val)
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m68k_switch_sp(env);
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}
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uint32_t HELPER(shl_cc)(CPUM68KState *env, uint32_t val, uint32_t shift)
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{
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uint64_t result;
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shift &= 63;
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result = (uint64_t)val << shift;
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env->cc_c = (result >> 32) & 1;
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env->cc_n = result;
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env->cc_z = result;
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env->cc_v = 0;
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env->cc_x = shift ? env->cc_c : env->cc_x;
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return result;
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}
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uint32_t HELPER(shr_cc)(CPUM68KState *env, uint32_t val, uint32_t shift)
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{
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uint64_t temp;
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uint32_t result;
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shift &= 63;
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temp = (uint64_t)val << 32 >> shift;
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result = temp >> 32;
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env->cc_c = (temp >> 31) & 1;
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env->cc_n = result;
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env->cc_z = result;
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env->cc_v = 0;
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env->cc_x = shift ? env->cc_c : env->cc_x;
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return result;
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}
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uint32_t HELPER(sar_cc)(CPUM68KState *env, uint32_t val, uint32_t shift)
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{
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uint64_t temp;
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uint32_t result;
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shift &= 63;
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temp = (int64_t)val << 32 >> shift;
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result = temp >> 32;
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env->cc_c = (temp >> 31) & 1;
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env->cc_n = result;
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env->cc_z = result;
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env->cc_v = result ^ val;
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env->cc_x = shift ? env->cc_c : env->cc_x;
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return result;
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}
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/* FPU helpers. */
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uint32_t HELPER(f64_to_i32)(CPUM68KState *env, float64 val)
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{
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@ -9,9 +9,6 @@ DEF_HELPER_4(divul, void, env, int, int, i32)
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DEF_HELPER_4(divsl, void, env, int, int, s32)
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DEF_HELPER_4(divull, void, env, int, int, i32)
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DEF_HELPER_4(divsll, void, env, int, int, s32)
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DEF_HELPER_3(shl_cc, i32, env, i32, i32)
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DEF_HELPER_3(shr_cc, i32, env, i32, i32)
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DEF_HELPER_3(sar_cc, i32, env, i32, i32)
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DEF_HELPER_2(set_sr, void, env, i32)
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DEF_HELPER_3(movec, void, env, i32, i32)
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DEF_HELPER_4(cas2w, void, env, i32, i32, i32)
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@ -2987,50 +2987,238 @@ DISAS_INSN(addx_mem)
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gen_store(s, opsize, addr_dest, tcg_ctx->QREG_CC_N);
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}
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/* TODO: This could be implemented without helper functions. */
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DISAS_INSN(shift_im)
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static inline void shift_im(DisasContext *s, uint16_t insn, int opsize)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv reg;
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int tmp;
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TCGv shift;
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TCGv QREG_CC_Z = tcg_ctx->QREG_CC_Z;
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TCGv QREG_CC_N = tcg_ctx->QREG_CC_N;
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TCGv QREG_CC_X = tcg_ctx->QREG_CC_X;
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TCGv QREG_CC_V = tcg_ctx->QREG_CC_V;
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TCGv QREG_CC_C = tcg_ctx->QREG_CC_C;
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set_cc_op(s, CC_OP_FLAGS);
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int count = (insn >> 9) & 7;
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int logical = insn & 8;
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int left = insn & 0x100;
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int bits = opsize_bytes(opsize) * 8;
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TCGv reg = gen_extend(s, DREG(insn, 0), opsize, !logical);
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reg = DREG(insn, 0);
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tmp = (insn >> 9) & 7;
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if (tmp == 0)
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tmp = 8;
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shift = tcg_const_i32(tcg_ctx, tmp);
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/* No need to flush flags becuse we know we will set C flag. */
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if (insn & 0x100) {
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gen_helper_shl_cc(tcg_ctx, reg, tcg_ctx->cpu_env, reg, shift);
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if (count == 0) {
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count = 8;
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}
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tcg_gen_movi_i32(tcg_ctx, QREG_CC_V, 0);
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if (left) {
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tcg_gen_shri_i32(tcg_ctx, QREG_CC_C, reg, bits - count);
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tcg_gen_shli_i32(tcg_ctx, QREG_CC_N, reg, count);
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/* Note that ColdFire always clears V (done above),
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while M68000 sets if the most significant bit is changed at
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any time during the shift operation */
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if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
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/* if shift count >= bits, V is (reg != 0) */
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if (count >= bits) {
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tcg_gen_setcond_i32(tcg_ctx, TCG_COND_NE, QREG_CC_V, reg, QREG_CC_V);
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} else {
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TCGv t0 = tcg_temp_new(tcg_ctx);
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tcg_gen_sari_i32(tcg_ctx, QREG_CC_V, reg, bits - 1);
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tcg_gen_sari_i32(tcg_ctx, t0, reg, bits - count - 1);
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tcg_gen_setcond_i32(tcg_ctx, TCG_COND_NE, QREG_CC_V, QREG_CC_V, t0);
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tcg_temp_free(tcg_ctx, t0);
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}
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tcg_gen_neg_i32(tcg_ctx, QREG_CC_V, QREG_CC_V);
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}
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} else {
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if (insn & 8) {
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gen_helper_shr_cc(tcg_ctx, reg, tcg_ctx->cpu_env, reg, shift);
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tcg_gen_shri_i32(tcg_ctx, QREG_CC_C, reg, count - 1);
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if (logical) {
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tcg_gen_shri_i32(tcg_ctx, QREG_CC_N, reg, count);
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} else {
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gen_helper_sar_cc(tcg_ctx, reg, tcg_ctx->cpu_env, reg, shift);
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tcg_gen_sari_i32(tcg_ctx, QREG_CC_N, reg, count);
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}
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}
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gen_ext(s, QREG_CC_N, QREG_CC_N, opsize, 1);
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tcg_gen_andi_i32(tcg_ctx, QREG_CC_C, QREG_CC_C, 1);
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tcg_gen_mov_i32(tcg_ctx, QREG_CC_Z, QREG_CC_N);
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tcg_gen_mov_i32(tcg_ctx, QREG_CC_X, QREG_CC_C);
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gen_partset_reg(s, opsize, DREG(insn, 0), QREG_CC_N);
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set_cc_op(s, CC_OP_FLAGS);
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}
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static inline void shift_reg(DisasContext *s, uint16_t insn, int opsize)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv QREG_CC_Z = tcg_ctx->QREG_CC_Z;
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TCGv QREG_CC_N = tcg_ctx->QREG_CC_N;
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TCGv QREG_CC_X = tcg_ctx->QREG_CC_X;
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TCGv QREG_CC_V = tcg_ctx->QREG_CC_V;
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TCGv QREG_CC_C = tcg_ctx->QREG_CC_C;
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int logical = insn & 8;
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int left = insn & 0x100;
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int bits = opsize_bytes(opsize) * 8;
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TCGv reg = gen_extend(s, DREG(insn, 0), opsize, !logical);
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TCGv s32;
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TCGv_i64 t64, s64;
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t64 = tcg_temp_new_i64(tcg_ctx);
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s64 = tcg_temp_new_i64(tcg_ctx);
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s32 = tcg_temp_new(tcg_ctx);
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/* Note that m68k truncates the shift count modulo 64, not 32.
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In addition, a 64-bit shift makes it easy to find "the last
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bit shifted out", for the carry flag. */
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tcg_gen_andi_i32(tcg_ctx, s32, DREG(insn, 9), 63);
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tcg_gen_extu_i32_i64(tcg_ctx, s64, s32);
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tcg_gen_extu_i32_i64(tcg_ctx, t64, reg);
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/* Optimistically set V=0. Also used as a zero source below. */
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tcg_gen_movi_i32(tcg_ctx, QREG_CC_V, 0);
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if (left) {
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tcg_gen_shl_i64(tcg_ctx, t64, t64, s64);
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if (opsize == OS_LONG) {
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tcg_gen_extr_i64_i32(tcg_ctx, QREG_CC_N, QREG_CC_C, t64);
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/* Note that C=0 if shift count is 0, and we get that for free. */
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} else {
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TCGv zero = tcg_const_i32(tcg_ctx, 0);
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tcg_gen_extrl_i64_i32(tcg_ctx, QREG_CC_N, t64);
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tcg_gen_shri_i32(tcg_ctx, QREG_CC_C, QREG_CC_N, bits);
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tcg_gen_movcond_i32(tcg_ctx, TCG_COND_EQ, QREG_CC_C,
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s32, zero, zero, QREG_CC_C);
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tcg_temp_free(tcg_ctx, zero);
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}
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tcg_gen_andi_i32(tcg_ctx, QREG_CC_C, QREG_CC_C, 1);
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/* X = C, but only if the shift count was non-zero. */
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tcg_gen_movcond_i32(tcg_ctx, TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V,
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QREG_CC_C, QREG_CC_X);
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/* M68000 sets V if the most significant bit is changed at
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* any time during the shift operation. Do this via creating
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* an extension of the sign bit, comparing, and discarding
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* the bits below the sign bit. I.e.
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* int64_t s = (intN_t)reg;
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* int64_t t = (int64_t)(intN_t)reg << count;
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* V = ((s ^ t) & (-1 << (bits - 1))) != 0
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*/
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if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
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TCGv_i64 tt = tcg_const_i64(tcg_ctx, 32);
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/* if shift is greater than 32, use 32 */
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tcg_gen_movcond_i64(tcg_ctx, TCG_COND_GT, s64, s64, tt, tt, s64);
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tcg_temp_free_i64(tcg_ctx, tt);
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/* Sign extend the input to 64 bits; re-do the shift. */
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tcg_gen_ext_i32_i64(tcg_ctx, t64, reg);
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tcg_gen_shl_i64(tcg_ctx, s64, t64, s64);
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/* Clear all bits that are unchanged. */
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tcg_gen_xor_i64(tcg_ctx, t64, t64, s64);
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/* Ignore the bits below the sign bit. */
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tcg_gen_andi_i64(tcg_ctx, t64, t64, -1ULL << (bits - 1));
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/* If any bits remain set, we have overflow. */
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tcg_gen_setcondi_i64(tcg_ctx, TCG_COND_NE, t64, t64, 0);
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tcg_gen_extrl_i64_i32(tcg_ctx, QREG_CC_V, t64);
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tcg_gen_neg_i32(tcg_ctx, QREG_CC_V, QREG_CC_V);
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}
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} else {
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tcg_gen_shli_i64(tcg_ctx, t64, t64, 32);
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if (logical) {
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tcg_gen_shr_i64(tcg_ctx, t64, t64, s64);
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} else {
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tcg_gen_sar_i64(tcg_ctx, t64, t64, s64);
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}
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tcg_gen_extr_i64_i32(tcg_ctx, QREG_CC_C, QREG_CC_N, t64);
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/* Note that C=0 if shift count is 0, and we get that for free. */
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tcg_gen_shri_i32(tcg_ctx, QREG_CC_C, QREG_CC_C, 31);
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/* X = C, but only if the shift count was non-zero. */
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tcg_gen_movcond_i32(tcg_ctx, TCG_COND_NE, QREG_CC_X, s32, QREG_CC_V,
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QREG_CC_C, QREG_CC_X);
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}
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gen_ext(s, QREG_CC_N, QREG_CC_N, opsize, 1);
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tcg_gen_mov_i32(tcg_ctx, QREG_CC_Z, QREG_CC_N);
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tcg_temp_free(tcg_ctx, s32);
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tcg_temp_free_i64(tcg_ctx, s64);
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tcg_temp_free_i64(tcg_ctx, t64);
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/* Write back the result. */
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gen_partset_reg(s, opsize, DREG(insn, 0), QREG_CC_N);
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set_cc_op(s, CC_OP_FLAGS);
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}
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DISAS_INSN(shift8_im)
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{
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shift_im(s, insn, OS_BYTE);
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}
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DISAS_INSN(shift16_im)
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{
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shift_im(s, insn, OS_WORD);
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}
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DISAS_INSN(shift_im)
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{
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shift_im(s, insn, OS_LONG);
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}
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DISAS_INSN(shift8_reg)
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{
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shift_reg(s, insn, OS_BYTE);
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}
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DISAS_INSN(shift16_reg)
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{
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shift_reg(s, insn, OS_WORD);
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}
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DISAS_INSN(shift_reg)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv reg;
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TCGv shift;
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shift_reg(s, insn, OS_LONG);
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}
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reg = DREG(insn, 0);
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shift = DREG(insn, 9);
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if (insn & 0x100) {
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gen_helper_shl_cc(tcg_ctx, reg, tcg_ctx->cpu_env, reg, shift);
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DISAS_INSN(shift_mem)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv QREG_CC_Z = tcg_ctx->QREG_CC_Z;
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TCGv QREG_CC_N = tcg_ctx->QREG_CC_N;
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TCGv QREG_CC_X = tcg_ctx->QREG_CC_X;
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TCGv QREG_CC_V = tcg_ctx->QREG_CC_V;
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TCGv QREG_CC_C = tcg_ctx->QREG_CC_C;
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int logical = insn & 8;
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int left = insn & 0x100;
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TCGv src;
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TCGv addr;
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SRC_EA(env, src, OS_WORD, !logical, &addr);
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tcg_gen_movi_i32(tcg_ctx, QREG_CC_V, 0);
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if (left) {
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tcg_gen_shri_i32(tcg_ctx, QREG_CC_C, src, 15);
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tcg_gen_shli_i32(tcg_ctx, QREG_CC_N, src, 1);
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/* Note that ColdFire always clears V,
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while M68000 sets if the most significant bit is changed at
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any time during the shift operation */
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if (!logical && m68k_feature(s->env, M68K_FEATURE_M68000)) {
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src = gen_extend(s, src, OS_WORD, 1);
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tcg_gen_xor_i32(tcg_ctx, QREG_CC_V, QREG_CC_N, src);
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}
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} else {
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if (insn & 8) {
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gen_helper_shr_cc(tcg_ctx, reg, tcg_ctx->cpu_env, reg, shift);
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tcg_gen_mov_i32(tcg_ctx, QREG_CC_C, src);
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if (logical) {
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tcg_gen_shri_i32(tcg_ctx, QREG_CC_N, src, 1);
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} else {
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gen_helper_sar_cc(tcg_ctx, reg, tcg_ctx->cpu_env, reg, shift);
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tcg_gen_sari_i32(tcg_ctx, QREG_CC_N, src, 1);
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}
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}
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gen_ext(s, QREG_CC_N, QREG_CC_N, OS_WORD, 1);
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tcg_gen_andi_i32(tcg_ctx, QREG_CC_C, QREG_CC_C, 1);
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tcg_gen_mov_i32(tcg_ctx, QREG_CC_Z, QREG_CC_N);
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tcg_gen_mov_i32(tcg_ctx, QREG_CC_X, QREG_CC_C);
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DEST_EA(env, insn, OS_WORD, QREG_CC_N, &addr);
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set_cc_op(s, CC_OP_FLAGS);
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}
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@ -4141,6 +4329,13 @@ void register_m68k_insns (CPUM68KState *env)
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INSN(adda, d0c0, f0c0, M68000);
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INSN(shift_im, e080, f0f0, CF_ISA_A);
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INSN(shift_reg, e0a0, f0f0, CF_ISA_A);
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INSN(shift8_im, e000, f0f0, M68000);
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INSN(shift16_im, e040, f0f0, M68000);
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INSN(shift_im, e080, f0f0, M68000);
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INSN(shift8_reg, e020, f0f0, M68000);
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INSN(shift16_reg, e060, f0f0, M68000);
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INSN(shift_reg, e0a0, f0f0, M68000);
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INSN(shift_mem, e0c0, fcc0, M68000);
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INSN(undef_fpu, f000, f000, CF_ISA_A);
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INSN(fpu, f200, ffc0, CF_FPU);
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INSN(fbcc, f280, ffc0, CF_FPU);
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