yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2024-12-23 01:15:37 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/riscv: vector integer divide instructions

Browse source 
Backports 85e6658cfe9d71cc207a710ffdf0e6546f8612aa
This commit is contained in:
LIU Zhiwei 2021-03-05 09:01:29 -05:00 committed by Lioncash
parent 14d06ee38c
commit d144afdc45
7 changed files with 221 additions and 0 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

32
qemu/header_gen.py
View file

@ -6723,6 +6723,38 @@ riscv_symbols = (
'helper_vmsgt_vx_h',
'helper_vmsgt_vx_w',
'helper_vmsgt_vx_d',
'helper_vdivu_vv_b',
'helper_vdivu_vv_h',
'helper_vdivu_vv_w',
'helper_vdivu_vv_d',
'helper_vdiv_vv_b',
'helper_vdiv_vv_h',
'helper_vdiv_vv_w',
'helper_vdiv_vv_d',
'helper_vremu_vv_b',
'helper_vremu_vv_h',
'helper_vremu_vv_w',
'helper_vremu_vv_d',
'helper_vrem_vv_b',
'helper_vrem_vv_h',
'helper_vrem_vv_w',
'helper_vrem_vv_d',
'helper_vdivu_vx_b',
'helper_vdivu_vx_h',
'helper_vdivu_vx_w',
'helper_vdivu_vx_d',
'helper_vdiv_vx_b',
'helper_vdiv_vx_h',
'helper_vdiv_vx_w',
'helper_vdiv_vx_d',
'helper_vremu_vx_b',
'helper_vremu_vx_h',
'helper_vremu_vx_w',
'helper_vremu_vx_d',
'helper_vrem_vx_b',
'helper_vrem_vx_h',
'helper_vrem_vx_w',
'helper_vrem_vx_d',
'pmp_hart_has_privs',
'pmpaddr_csr_read',
'pmpaddr_csr_write',

32
qemu/riscv32.h
View file

@ -4159,6 +4159,38 @@
#define helper_vmsgt_vx_h helper_vmsgt_vx_h_riscv32
#define helper_vmsgt_vx_w helper_vmsgt_vx_w_riscv32
#define helper_vmsgt_vx_d helper_vmsgt_vx_d_riscv32
#define helper_vdivu_vv_b helper_vdivu_vv_b_riscv32
#define helper_vdivu_vv_h helper_vdivu_vv_h_riscv32
#define helper_vdivu_vv_w helper_vdivu_vv_w_riscv32
#define helper_vdivu_vv_d helper_vdivu_vv_d_riscv32
#define helper_vdiv_vv_b helper_vdiv_vv_b_riscv32
#define helper_vdiv_vv_h helper_vdiv_vv_h_riscv32
#define helper_vdiv_vv_w helper_vdiv_vv_w_riscv32
#define helper_vdiv_vv_d helper_vdiv_vv_d_riscv32
#define helper_vremu_vv_b helper_vremu_vv_b_riscv32
#define helper_vremu_vv_h helper_vremu_vv_h_riscv32
#define helper_vremu_vv_w helper_vremu_vv_w_riscv32
#define helper_vremu_vv_d helper_vremu_vv_d_riscv32
#define helper_vrem_vv_b helper_vrem_vv_b_riscv32
#define helper_vrem_vv_h helper_vrem_vv_h_riscv32
#define helper_vrem_vv_w helper_vrem_vv_w_riscv32
#define helper_vrem_vv_d helper_vrem_vv_d_riscv32
#define helper_vdivu_vx_b helper_vdivu_vx_b_riscv32
#define helper_vdivu_vx_h helper_vdivu_vx_h_riscv32
#define helper_vdivu_vx_w helper_vdivu_vx_w_riscv32
#define helper_vdivu_vx_d helper_vdivu_vx_d_riscv32
#define helper_vdiv_vx_b helper_vdiv_vx_b_riscv32
#define helper_vdiv_vx_h helper_vdiv_vx_h_riscv32
#define helper_vdiv_vx_w helper_vdiv_vx_w_riscv32
#define helper_vdiv_vx_d helper_vdiv_vx_d_riscv32
#define helper_vremu_vx_b helper_vremu_vx_b_riscv32
#define helper_vremu_vx_h helper_vremu_vx_h_riscv32
#define helper_vremu_vx_w helper_vremu_vx_w_riscv32
#define helper_vremu_vx_d helper_vremu_vx_d_riscv32
#define helper_vrem_vx_b helper_vrem_vx_b_riscv32
#define helper_vrem_vx_h helper_vrem_vx_h_riscv32
#define helper_vrem_vx_w helper_vrem_vx_w_riscv32
#define helper_vrem_vx_d helper_vrem_vx_d_riscv32
#define pmp_hart_has_privs pmp_hart_has_privs_riscv32
#define pmpaddr_csr_read pmpaddr_csr_read_riscv32
#define pmpaddr_csr_write pmpaddr_csr_write_riscv32

32
qemu/riscv64.h
View file

@ -4159,6 +4159,38 @@
#define helper_vmsgt_vx_h helper_vmsgt_vx_h_riscv64
#define helper_vmsgt_vx_w helper_vmsgt_vx_w_riscv64
#define helper_vmsgt_vx_d helper_vmsgt_vx_d_riscv64
#define helper_vdivu_vv_b helper_vdivu_vv_b_riscv64
#define helper_vdivu_vv_h helper_vdivu_vv_h_riscv64
#define helper_vdivu_vv_w helper_vdivu_vv_w_riscv64
#define helper_vdivu_vv_d helper_vdivu_vv_d_riscv64
#define helper_vdiv_vv_b helper_vdiv_vv_b_riscv64
#define helper_vdiv_vv_h helper_vdiv_vv_h_riscv64
#define helper_vdiv_vv_w helper_vdiv_vv_w_riscv64
#define helper_vdiv_vv_d helper_vdiv_vv_d_riscv64
#define helper_vremu_vv_b helper_vremu_vv_b_riscv64
#define helper_vremu_vv_h helper_vremu_vv_h_riscv64
#define helper_vremu_vv_w helper_vremu_vv_w_riscv64
#define helper_vremu_vv_d helper_vremu_vv_d_riscv64
#define helper_vrem_vv_b helper_vrem_vv_b_riscv64
#define helper_vrem_vv_h helper_vrem_vv_h_riscv64
#define helper_vrem_vv_w helper_vrem_vv_w_riscv64
#define helper_vrem_vv_d helper_vrem_vv_d_riscv64
#define helper_vdivu_vx_b helper_vdivu_vx_b_riscv64
#define helper_vdivu_vx_h helper_vdivu_vx_h_riscv64
#define helper_vdivu_vx_w helper_vdivu_vx_w_riscv64
#define helper_vdivu_vx_d helper_vdivu_vx_d_riscv64
#define helper_vdiv_vx_b helper_vdiv_vx_b_riscv64
#define helper_vdiv_vx_h helper_vdiv_vx_h_riscv64
#define helper_vdiv_vx_w helper_vdiv_vx_w_riscv64
#define helper_vdiv_vx_d helper_vdiv_vx_d_riscv64
#define helper_vremu_vx_b helper_vremu_vx_b_riscv64
#define helper_vremu_vx_h helper_vremu_vx_h_riscv64
#define helper_vremu_vx_w helper_vremu_vx_w_riscv64
#define helper_vremu_vx_d helper_vremu_vx_d_riscv64
#define helper_vrem_vx_b helper_vrem_vx_b_riscv64
#define helper_vrem_vx_h helper_vrem_vx_h_riscv64
#define helper_vrem_vx_w helper_vrem_vx_w_riscv64
#define helper_vrem_vx_d helper_vrem_vx_d_riscv64
#define pmp_hart_has_privs pmp_hart_has_privs_riscv64
#define pmpaddr_csr_read pmpaddr_csr_read_riscv64
#define pmpaddr_csr_write pmpaddr_csr_write_riscv64

33
qemu/target/riscv/helper.h
View file

@ -558,3 +558,36 @@ DEF_HELPER_6(vmulhsu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vmulhsu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vmulhsu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vmulhsu_vx_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vdivu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vdivu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vdivu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vdivu_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vdiv_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vdiv_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vdiv_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vdiv_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vremu_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vremu_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vremu_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vremu_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vrem_vv_b, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vrem_vv_h, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vrem_vv_w, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vrem_vv_d, void, ptr, ptr, ptr, ptr, env, i32)
DEF_HELPER_6(vdivu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vdivu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vdivu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vdivu_vx_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vdiv_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vdiv_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vdiv_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vdiv_vx_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vremu_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vremu_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vremu_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vremu_vx_d, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vrem_vx_b, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vrem_vx_h, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vrem_vx_w, void, ptr, ptr, tl, ptr, env, i32)
DEF_HELPER_6(vrem_vx_d, void, ptr, ptr, tl, ptr, env, i32)

8
qemu/target/riscv/insn32.decode
View file

@ -367,6 +367,14 @@ vmulhu_vv 100100 . ..... ..... 010 ..... 1010111 @r_vm
vmulhu_vx 100100 . ..... ..... 110 ..... 1010111 @r_vm
vmulhsu_vv 100110 . ..... ..... 010 ..... 1010111 @r_vm
vmulhsu_vx 100110 . ..... ..... 110 ..... 1010111 @r_vm
vdivu_vv 100000 . ..... ..... 010 ..... 1010111 @r_vm
vdivu_vx 100000 . ..... ..... 110 ..... 1010111 @r_vm
vdiv_vv 100001 . ..... ..... 010 ..... 1010111 @r_vm
vdiv_vx 100001 . ..... ..... 110 ..... 1010111 @r_vm
vremu_vv 100010 . ..... ..... 010 ..... 1010111 @r_vm
vremu_vx 100010 . ..... ..... 110 ..... 1010111 @r_vm
vrem_vv 100011 . ..... ..... 010 ..... 1010111 @r_vm
vrem_vx 100011 . ..... ..... 110 ..... 1010111 @r_vm
vsetvli 0 ........... ..... 111 ..... 1010111 @r2_zimm
vsetvl 1000000 ..... ..... 111 ..... 1010111 @r

10
qemu/target/riscv/insn_trans/trans_rvv.inc.c
View file

@ -1512,3 +1512,13 @@ GEN_OPIVX_GVEC_TRANS(vmul_vx, muls)
GEN_OPIVX_TRANS(vmulh_vx, opivx_check)
GEN_OPIVX_TRANS(vmulhu_vx, opivx_check)
GEN_OPIVX_TRANS(vmulhsu_vx, opivx_check)
/* Vector Integer Divide Instructions */
GEN_OPIVV_TRANS(vdivu_vv, opivv_check)
GEN_OPIVV_TRANS(vdiv_vv, opivv_check)
GEN_OPIVV_TRANS(vremu_vv, opivv_check)
GEN_OPIVV_TRANS(vrem_vv, opivv_check)
GEN_OPIVX_TRANS(vdivu_vx, opivx_check)
GEN_OPIVX_TRANS(vdiv_vx, opivx_check)
GEN_OPIVX_TRANS(vremu_vx, opivx_check)
GEN_OPIVX_TRANS(vrem_vx, opivx_check)

74
qemu/target/riscv/vector_helper.c
View file

@ -1753,3 +1753,77 @@ GEN_VEXT_VX(vmulhsu_vx_b, 1, 1, clearb)
GEN_VEXT_VX(vmulhsu_vx_h, 2, 2, clearh)
GEN_VEXT_VX(vmulhsu_vx_w, 4, 4, clearl)
GEN_VEXT_VX(vmulhsu_vx_d, 8, 8, clearq)
/* Vector Integer Divide Instructions */
#define DO_DIVU(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) : N / M)
#define DO_REMU(N, M) (unlikely(M == 0) ? N : N % M)
#define DO_DIV(N, M) (unlikely(M == 0) ? (__typeof(N))(-1) :\
unlikely((N == -N) && (M == (__typeof(N))(-1))) ? N : N / M)
#define DO_REM(N, M) (unlikely(M == 0) ? N :\
unlikely((N == -N) && (M == (__typeof(N))(-1))) ? 0 : N % M)
RVVCALL(OPIVV2, vdivu_vv_b, OP_UUU_B, H1, H1, H1, DO_DIVU)
RVVCALL(OPIVV2, vdivu_vv_h, OP_UUU_H, H2, H2, H2, DO_DIVU)
RVVCALL(OPIVV2, vdivu_vv_w, OP_UUU_W, H4, H4, H4, DO_DIVU)
RVVCALL(OPIVV2, vdivu_vv_d, OP_UUU_D, H8, H8, H8, DO_DIVU)
RVVCALL(OPIVV2, vdiv_vv_b, OP_SSS_B, H1, H1, H1, DO_DIV)
RVVCALL(OPIVV2, vdiv_vv_h, OP_SSS_H, H2, H2, H2, DO_DIV)
RVVCALL(OPIVV2, vdiv_vv_w, OP_SSS_W, H4, H4, H4, DO_DIV)
RVVCALL(OPIVV2, vdiv_vv_d, OP_SSS_D, H8, H8, H8, DO_DIV)
RVVCALL(OPIVV2, vremu_vv_b, OP_UUU_B, H1, H1, H1, DO_REMU)
RVVCALL(OPIVV2, vremu_vv_h, OP_UUU_H, H2, H2, H2, DO_REMU)
RVVCALL(OPIVV2, vremu_vv_w, OP_UUU_W, H4, H4, H4, DO_REMU)
RVVCALL(OPIVV2, vremu_vv_d, OP_UUU_D, H8, H8, H8, DO_REMU)
RVVCALL(OPIVV2, vrem_vv_b, OP_SSS_B, H1, H1, H1, DO_REM)
RVVCALL(OPIVV2, vrem_vv_h, OP_SSS_H, H2, H2, H2, DO_REM)
RVVCALL(OPIVV2, vrem_vv_w, OP_SSS_W, H4, H4, H4, DO_REM)
RVVCALL(OPIVV2, vrem_vv_d, OP_SSS_D, H8, H8, H8, DO_REM)
GEN_VEXT_VV(vdivu_vv_b, 1, 1, clearb)
GEN_VEXT_VV(vdivu_vv_h, 2, 2, clearh)
GEN_VEXT_VV(vdivu_vv_w, 4, 4, clearl)
GEN_VEXT_VV(vdivu_vv_d, 8, 8, clearq)
GEN_VEXT_VV(vdiv_vv_b, 1, 1, clearb)
GEN_VEXT_VV(vdiv_vv_h, 2, 2, clearh)
GEN_VEXT_VV(vdiv_vv_w, 4, 4, clearl)
GEN_VEXT_VV(vdiv_vv_d, 8, 8, clearq)
GEN_VEXT_VV(vremu_vv_b, 1, 1, clearb)
GEN_VEXT_VV(vremu_vv_h, 2, 2, clearh)
GEN_VEXT_VV(vremu_vv_w, 4, 4, clearl)
GEN_VEXT_VV(vremu_vv_d, 8, 8, clearq)
GEN_VEXT_VV(vrem_vv_b, 1, 1, clearb)
GEN_VEXT_VV(vrem_vv_h, 2, 2, clearh)
GEN_VEXT_VV(vrem_vv_w, 4, 4, clearl)
GEN_VEXT_VV(vrem_vv_d, 8, 8, clearq)
RVVCALL(OPIVX2, vdivu_vx_b, OP_UUU_B, H1, H1, DO_DIVU)
RVVCALL(OPIVX2, vdivu_vx_h, OP_UUU_H, H2, H2, DO_DIVU)
RVVCALL(OPIVX2, vdivu_vx_w, OP_UUU_W, H4, H4, DO_DIVU)
RVVCALL(OPIVX2, vdivu_vx_d, OP_UUU_D, H8, H8, DO_DIVU)
RVVCALL(OPIVX2, vdiv_vx_b, OP_SSS_B, H1, H1, DO_DIV)
RVVCALL(OPIVX2, vdiv_vx_h, OP_SSS_H, H2, H2, DO_DIV)
RVVCALL(OPIVX2, vdiv_vx_w, OP_SSS_W, H4, H4, DO_DIV)
RVVCALL(OPIVX2, vdiv_vx_d, OP_SSS_D, H8, H8, DO_DIV)
RVVCALL(OPIVX2, vremu_vx_b, OP_UUU_B, H1, H1, DO_REMU)
RVVCALL(OPIVX2, vremu_vx_h, OP_UUU_H, H2, H2, DO_REMU)
RVVCALL(OPIVX2, vremu_vx_w, OP_UUU_W, H4, H4, DO_REMU)
RVVCALL(OPIVX2, vremu_vx_d, OP_UUU_D, H8, H8, DO_REMU)
RVVCALL(OPIVX2, vrem_vx_b, OP_SSS_B, H1, H1, DO_REM)
RVVCALL(OPIVX2, vrem_vx_h, OP_SSS_H, H2, H2, DO_REM)
RVVCALL(OPIVX2, vrem_vx_w, OP_SSS_W, H4, H4, DO_REM)
RVVCALL(OPIVX2, vrem_vx_d, OP_SSS_D, H8, H8, DO_REM)
GEN_VEXT_VX(vdivu_vx_b, 1, 1, clearb)
GEN_VEXT_VX(vdivu_vx_h, 2, 2, clearh)
GEN_VEXT_VX(vdivu_vx_w, 4, 4, clearl)
GEN_VEXT_VX(vdivu_vx_d, 8, 8, clearq)
GEN_VEXT_VX(vdiv_vx_b, 1, 1, clearb)
GEN_VEXT_VX(vdiv_vx_h, 2, 2, clearh)
GEN_VEXT_VX(vdiv_vx_w, 4, 4, clearl)
GEN_VEXT_VX(vdiv_vx_d, 8, 8, clearq)
GEN_VEXT_VX(vremu_vx_b, 1, 1, clearb)
GEN_VEXT_VX(vremu_vx_h, 2, 2, clearh)
GEN_VEXT_VX(vremu_vx_w, 4, 4, clearl)
GEN_VEXT_VX(vremu_vx_d, 8, 8, clearq)
GEN_VEXT_VX(vrem_vx_b, 1, 1, clearb)
GEN_VEXT_VX(vrem_vx_h, 2, 2, clearh)
GEN_VEXT_VX(vrem_vx_w, 4, 4, clearl)
GEN_VEXT_VX(vrem_vx_d, 8, 8, clearq)