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target/arm: Rely on optimization within tcg_gen_gvec_or
Since we're now handling a == b generically, we no longer need to do it by hand within target/arm/. Backports commit 2900847ff4c862887af750935a875059615f509a from qemu
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@ -10807,11 +10807,7 @@ static void disas_simd_3same_logic(DisasContext *s, uint32_t insn)
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gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_andc, 0);
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return;
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case 2: /* ORR */
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if (rn == rm) { /* MOV */
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gen_gvec_fn2(s, is_q, rd, rn, tcg_gen_gvec_mov, 0);
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} else {
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gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_or, 0);
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}
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return;
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case 3: /* ORN */
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gen_gvec_fn3(s, is_q, rd, rn, rm, tcg_gen_gvec_orc, 0);
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@ -286,11 +286,7 @@ static bool trans_AND_zzz(DisasContext *s, arg_rrr_esz *a)
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static bool trans_ORR_zzz(DisasContext *s, arg_rrr_esz *a)
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{
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if (a->rn == a->rm) { /* MOV */
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return do_mov_z(s, a->rd, a->rn);
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} else {
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return do_vector3_z(s, tcg_gen_gvec_or, 0, a->rd, a->rn, a->rm);
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}
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}
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static bool trans_EOR_zzz(DisasContext *s, arg_rrr_esz *a)
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@ -6456,15 +6456,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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tcg_gen_gvec_andc(tcg_ctx, 0, rd_ofs, rn_ofs, rm_ofs,
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vec_size, vec_size);
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break;
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case 2:
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if (rn == rm) {
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/* VMOV */
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tcg_gen_gvec_mov(tcg_ctx, 0, rd_ofs, rn_ofs, vec_size, vec_size);
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} else {
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/* VORR */
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case 2: /* VORR */
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tcg_gen_gvec_or(tcg_ctx, 0, rd_ofs, rn_ofs, rm_ofs,
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vec_size, vec_size);
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}
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break;
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case 3: /* VORN */
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tcg_gen_gvec_orc(tcg_ctx, 0, rd_ofs, rn_ofs, rm_ofs,
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