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tcg/aarch64: Fix output of extract2 opcodes

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This patch fixes two problems:
(1) The inputs to the EXTR insn were reversed,
(2) The input constraints use rZ, which means that we need to use
the REG0 macro in order to supply XZR for a constant 0 input.

Fixes: 464c2969d5d

Backports commit 1789d4274b851fb8fdf4a947ce5474c63e813d0d from qemu
This commit is contained in:
Richard Henderson 2019-08-08 19:25:36 -04:00 committed by Lioncash
parent b2d75f4955
commit d291a311ee
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1 changed files with 1 additions and 1 deletions
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2
qemu/tcg/aarch64/tcg-target.inc.c
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@ -2228,7 +2228,7 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_extract2_i64:
case INDEX_op_extract2_i32:
tcg_out_extr(s, ext, a0, a1, a2, args[3]);
tcg_out_extr(s, ext, a0, REG0(2), REG0(1), args[3]);
break;
case INDEX_op_add2_i32: