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target/riscv: Fix implementation of HLVX.WU instruction

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The HLVX.WU instruction is supposed to read a machine word,
but prior to this change it read a byte instead.

Fixes: 8c5362acb57 ("target/riscv: Allow generating hlv/hlvx/hsv instructions")

Backports 1da46012eaaeb2feb3aa6a5a8fc0a03200b673aa
This commit is contained in:
Georg Kotheimer 2021-03-08 14:40:27 -05:00 committed by Lioncash
parent 7351f09919
commit d2cea344f0
1 changed files with 3 additions and 3 deletions
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6
qemu/target/riscv/op_helper.c
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@ -335,12 +335,12 @@ target_ulong helper_hyp_x_load(CPURISCVState *env, target_ulong address,
riscv_cpu_set_two_stage_lookup(env, true); riscv_cpu_set_two_stage_lookup(env, true);
switch (memop) { switch (memop) {
case MO_TEUL:
pte = cpu_ldl_mmuidx_ra(env, address, cpu_mmu_index(env, true), GETPC());
break;
case MO_TEUW: case MO_TEUW:
pte = cpu_lduw_mmuidx_ra(env, address, cpu_mmu_index(env, true), GETPC()); pte = cpu_lduw_mmuidx_ra(env, address, cpu_mmu_index(env, true), GETPC());
break; break;
case MO_TEUL:
pte = cpu_ldl_mmuidx_ra(env, address, cpu_mmu_index(env, true), GETPC());
break;
default: default:
g_assert_not_reached(); g_assert_not_reached();
} }