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target/arm: Stop using cpu_F0s in Neon VCVT fixed-point ops
Stop using cpu_F0s in the Neon VCVT fixed-point operations. Backports commit c253dd7832bc6b4e140a0da56410a9336cce05bc from qemu
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parent
46216ae382
commit
d419fbc270
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@ -65,6 +65,8 @@ static const char *regnames[] =
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/* Function prototypes for gen_ functions calling Neon helpers. */
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typedef void NeonGenThreeOpEnvFn(TCGContext *, TCGv_i32, TCGv_env, TCGv_i32,
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TCGv_i32, TCGv_i32);
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/* Function prototypes for gen_ functions for fix point conversions */
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typedef void VFPGenFixPointFn(TCGContext *, TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr);
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/* initialize TCG globals. */
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void arm_translate_init(struct uc_struct *uc)
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@ -1429,28 +1431,6 @@ static TCGv_ptr get_fpstatus_ptr(DisasContext *s, int neon)
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return statusptr;
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}
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#define VFP_GEN_FIX(name, round) \
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static inline void gen_vfp_##name(DisasContext *s, int dp, int shift, int neon) \
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{ \
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TCGContext *tcg_ctx = s->uc->tcg_ctx; \
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TCGv_i32 tmp_shift = tcg_const_i32(tcg_ctx, shift); \
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TCGv_ptr statusptr = get_fpstatus_ptr(s, neon); \
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if (dp) { \
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gen_helper_vfp_##name##d##round(tcg_ctx, s->F0d, s->F0d, tmp_shift, \
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statusptr); \
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} else { \
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gen_helper_vfp_##name##s##round(tcg_ctx, s->F0s, s->F0s, tmp_shift, \
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statusptr); \
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} \
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tcg_temp_free_i32(tcg_ctx, tmp_shift); \
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tcg_temp_free_ptr(tcg_ctx, statusptr); \
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}
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VFP_GEN_FIX(tosl, _round_to_zero)
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VFP_GEN_FIX(toul, _round_to_zero)
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VFP_GEN_FIX(slto, )
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VFP_GEN_FIX(ulto, )
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#undef VFP_GEN_FIX
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static inline long vfp_reg_offset(bool dp, unsigned reg)
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{
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if (dp) {
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@ -5856,28 +5836,41 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
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}
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} else if (op >= 14) {
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/* VCVT fixed-point. */
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TCGv_ptr fpst;
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TCGv_i32 shiftv;
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VFPGenFixPointFn *fn;
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if (!(insn & (1 << 21)) || (q && ((rd | rm) & 1))) {
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return 1;
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}
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if (!(op & 1)) {
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if (u) {
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fn = gen_helper_vfp_ultos;
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} else {
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fn = gen_helper_vfp_sltos;
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}
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} else {
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if (u) {
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fn = gen_helper_vfp_touls_round_to_zero;
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} else {
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fn = gen_helper_vfp_tosls_round_to_zero;
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}
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}
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/* We have already masked out the must-be-1 top bit of imm6,
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* hence this 32-shift where the ARM ARM has 64-imm6.
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*/
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shift = 32 - shift;
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fpst = get_fpstatus_ptr(s, 1);
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shiftv = tcg_const_i32(tcg_ctx, shift);
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for (pass = 0; pass < (q ? 4 : 2); pass++) {
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tcg_gen_ld_f32(tcg_ctx, s->F0s, tcg_ctx->cpu_env, neon_reg_offset(rm, pass));
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if (!(op & 1)) {
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if (u)
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gen_vfp_ulto(s, 0, shift, 1);
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else
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gen_vfp_slto(s, 0, shift, 1);
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} else {
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if (u)
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gen_vfp_toul(s, 0, shift, 1);
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else
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gen_vfp_tosl(s, 0, shift, 1);
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}
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tcg_gen_st_f32(tcg_ctx, s->F0s, tcg_ctx->cpu_env, neon_reg_offset(rd, pass));
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TCGv_i32 tmpf = neon_load_reg(s, rm, pass);
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fn(tcg_ctx, tmpf, tmpf, shiftv, fpst);
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neon_store_reg(s, rd, pass, tmpf);
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}
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tcg_temp_free_ptr(tcg_ctx, fpst);
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tcg_temp_free_i32(tcg_ctx, shiftv);
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} else {
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return 1;
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}
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