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target/riscv: Emulate TIME CSRs for privileged mode

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Currently, TIME CSRs are emulated only for user-only mode. This
patch add TIME CSRs emulation for privileged mode.

For privileged mode, the TIME CSRs will return value provided
by rdtime callback which is registered by QEMU machine/platform
emulation (i.e. CLINT emulation). If rdtime callback is not
available then the monitor (i.e. OpenSBI) will trap-n-emulate
TIME CSRs in software.

We see 25+% performance improvement in hackbench numbers when
TIME CSRs are not trap-n-emulated.

Backports commit c695724868ce4049fd79c5a509880dbdf171e744 from qemu
This commit is contained in:
Anup Patel 2020-03-22 02:21:27 -04:00 committed by Lioncash
parent 6c3338430a
commit d47390ade4
6 changed files with 95 additions and 4 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

1
qemu/header_gen.py
View file

@ -5575,6 +5575,7 @@ riscv_symbols = (
'riscv_cpu_set_fflags',
'riscv_cpu_set_force_hs_excep',
'riscv_cpu_set_mode',
'riscv_cpu_set_rdtime_fn',
'riscv_cpu_set_virt_enabled',
'riscv_cpu_swap_hypervisor_regs',
'riscv_cpu_tlb_fill',

1
qemu/riscv32.h
View file

@ -3462,6 +3462,7 @@
#define riscv_cpu_set_fflags riscv_cpu_set_fflags_riscv32
#define riscv_cpu_set_force_hs_excep riscv_cpu_set_force_hs_excep_riscv32
#define riscv_cpu_set_mode riscv_cpu_set_mode_riscv32
#define riscv_cpu_set_rdtime_fn riscv_cpu_set_rdtime_fn_riscv32
#define riscv_cpu_set_virt_enabled riscv_cpu_set_virt_enabled_riscv32
#define riscv_cpu_swap_hypervisor_regs riscv_cpu_swap_hypervisor_regs_riscv32
#define riscv_cpu_tlb_fill riscv_cpu_tlb_fill_riscv32

1
qemu/riscv64.h
View file

@ -3462,6 +3462,7 @@
#define riscv_cpu_set_fflags riscv_cpu_set_fflags_riscv64
#define riscv_cpu_set_force_hs_excep riscv_cpu_set_force_hs_excep_riscv64
#define riscv_cpu_set_mode riscv_cpu_set_mode_riscv64
#define riscv_cpu_set_rdtime_fn riscv_cpu_set_rdtime_fn_riscv64
#define riscv_cpu_set_virt_enabled riscv_cpu_set_virt_enabled_riscv64
#define riscv_cpu_swap_hypervisor_regs riscv_cpu_swap_hypervisor_regs_riscv64
#define riscv_cpu_tlb_fill riscv_cpu_tlb_fill_riscv64

5
qemu/target/riscv/cpu.h
View file

@ -174,6 +174,7 @@ struct CPURISCVState {
target_ulong htval;
target_ulong htinst;
target_ulong hgatp;
uint64_t htimedelta;
/* Virtual CSRs */
target_ulong vsstatus;
@ -216,6 +217,9 @@ struct CPURISCVState {
/* physical memory protection */
pmp_table_t pmp_state;
/* machine specific rdtime callback */
uint64_t (*rdtime_fn)(void);
/* True if in debugger mode. */
bool debugger;
#endif
@ -322,6 +326,7 @@ void riscv_cpu_swap_hypervisor_regs(CPURISCVState *env);
int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts);
uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value);
#define BOOL_TO_MASK(x) (-!!(x)) /* helper for riscv_cpu_update_mip value */
void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void));
#endif
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv);

5
qemu/target/riscv/cpu_helper.c
View file

@ -252,6 +252,11 @@ uint32_t riscv_cpu_update_mip(RISCVCPU *cpu, uint32_t mask, uint32_t value)
return old;
}
void riscv_cpu_set_rdtime_fn(CPURISCVState *env, uint64_t (*fn)(void))
{
env->rdtime_fn = fn;
}
void riscv_cpu_set_mode(CPURISCVState *env, target_ulong newpriv)
{
if (newpriv > PRV_M) {

86
qemu/target/riscv/csr.c
View file

@ -238,6 +238,32 @@ static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
#else /* CONFIG_USER_ONLY */
static int read_time(CPURISCVState *env, int csrno, target_ulong *val)
{
uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
if (!env->rdtime_fn) {
return -1;
}
*val = env->rdtime_fn() + delta;
return 0;
}
#if defined(TARGET_RISCV32)
static int read_timeh(CPURISCVState *env, int csrno, target_ulong *val)
{
uint64_t delta = riscv_cpu_virt_enabled(env) ? env->htimedelta : 0;
if (!env->rdtime_fn) {
return -1;
}
*val = (env->rdtime_fn() + delta) >> 32;
return 0;
}
#endif
/* Machine constants */
#define M_MODE_INTERRUPTS (MIP_MSIP | MIP_MTIP | MIP_MEIP)
@ -933,6 +959,56 @@ static int write_hgatp(CPURISCVState *env, int csrno, target_ulong val)
return 0;
}
static int read_htimedelta(CPURISCVState *env, int csrno, target_ulong *val)
{
if (!env->rdtime_fn) {
return -1;
}
#if defined(TARGET_RISCV32)
*val = env->htimedelta & 0xffffffff;
#else
*val = env->htimedelta;
#endif
return 0;
}
static int write_htimedelta(CPURISCVState *env, int csrno, target_ulong val)
{
if (!env->rdtime_fn) {
return -1;
}
#if defined(TARGET_RISCV32)
env->htimedelta = deposit64(env->htimedelta, 0, 32, (uint64_t)val);
#else
env->htimedelta = val;
#endif
return 0;
}
#if defined(TARGET_RISCV32)
static int read_htimedeltah(CPURISCVState *env, int csrno, target_ulong *val)
{
if (!env->rdtime_fn) {
return -1;
}
*val = env->htimedelta >> 32;
return 0;
}
static int write_htimedeltah(CPURISCVState *env, int csrno, target_ulong val)
{
if (!env->rdtime_fn) {
return -1;
}
env->htimedelta = deposit64(env->htimedelta, 32, 32, (uint64_t)val);
return 0;
}
#endif
/* Virtual CSR Registers */
static int read_vsstatus(CPURISCVState *env, int csrno, target_ulong *val)
{
@ -1203,14 +1279,12 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_INSTRETH] = { ctr, read_instreth },
#endif
/* User-level time CSRs are only available in linux-user
* In privileged mode, the monitor emulates these CSRs */
#if defined(CONFIG_USER_ONLY)
/* In privileged mode, the monitor will have to emulate TIME CSRs only if
* rdtime callback is not provided by machine/platform emulation */
[CSR_TIME] = { ctr, read_time },
#if defined(TARGET_RISCV32)
[CSR_TIMEH] = { ctr, read_timeh },
#endif
#endif
#if !defined(CONFIG_USER_ONLY)
/* Machine Timers and Counters */
@ -1276,6 +1350,10 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_HTVAL] = { hmode, read_htval, write_htval },
[CSR_HTINST] = { hmode, read_htinst, write_htinst },
[CSR_HGATP] = { hmode, read_hgatp, write_hgatp },
[CSR_HTIMEDELTA] = { hmode, read_htimedelta, write_htimedelta },
#if defined(TARGET_RISCV32)
[CSR_HTIMEDELTAH] = { hmode, read_htimedeltah, write_htimedeltah},
#endif
[CSR_VSSTATUS] = { hmode, read_vsstatus, write_vsstatus },
[CSR_VSIP] = { hmode, NULL, NULL, rmw_vsip },