target/riscv: cpu: Add a new 'resetvec' property

Currently the reset vector address is hard-coded in a RISC-V CPU's
instance_init() routine. In a real world we can have 2 exact same
CPUs except for the reset vector address, which is pretty common in
the RISC-V core IP licensing business.

Normally reset vector address is a configurable parameter. Let's
create a 64-bit property to store the reset vector address which
covers both 32-bit and 64-bit CPUs.

Backports 9b4c9b2b2a50fe4eb90d0ac2d8723b46ecb42511

qemu/target/riscv/cpu.h

@@ -294,6 +294,7 @@ typedef struct RISCVCPU {
         char *vext_spec;
         uint16_t vlen;
         uint16_t elen;
+        uint64_t resetvec;
     } cfg;
 } RISCVCPU;