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target/mips: Preparing for adding MMI instructions

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Set up MMI code to be compiled only for TARGET_MIPS64. This is
needed so that GPRs are 64 bit, and combined with MMI registers,
they will form full 128 bit registers.

Backports commit 37b9aae2e6e005e6df206a0b4804972460806166 from qemu
This commit is contained in:
Mateja Marjanovic 2019-02-28 16:06:14 -05:00 committed by Lioncash
parent fbe1ee25ff
commit d50a1fef6b
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 41 additions and 2 deletions
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43
qemu/target/mips/translate.c
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@ -4398,6 +4398,7 @@ static void gen_shift(DisasContext *ctx, uint32_t opc,
tcg_temp_free(tcg_ctx, t1);
}
#if defined(TARGET_MIPS64)
/* Copy GPR to and from TX79 HI1/LO1 register. */
static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg)
{
@ -4435,6 +4436,7 @@ static void gen_HILO1_tx79(DisasContext *ctx, uint32_t opc, int reg)
break;
}
}
#endif
/* Arithmetic on HI/LO registers */
static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg)
@ -4794,6 +4796,7 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt)
tcg_temp_free(tcg_ctx, t1);
}
#if defined(TARGET_MIPS64)
static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
@ -4851,6 +4854,7 @@ static void gen_div1_tx79(DisasContext *ctx, uint32_t opc, int rs, int rt)
tcg_temp_free(tcg_ctx, t0);
tcg_temp_free(tcg_ctx, t1);
}
#endif
static void gen_muldiv(DisasContext *ctx, uint32_t opc,
int acc, int rs, int rt)
@ -24463,6 +24467,29 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx)
}
#if defined(TARGET_MIPS64)
/*
*
* MMI (MultiMedia Interface) ASE instructions
* ===========================================
*/
/*
* MMI instructions category: data communication
* ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
*
* PCPYH PEXCH PEXTLB PINTH PPACB PEXT5 PREVH
* PCPYLD PEXCW PEXTLH PINTEH PPACH PPAC5 PROT3W
* PCPYUD PEXEH PEXTLW PPACW
* PEXEW PEXTUB
* PEXTUH
* PEXTUW
*/
#endif
#if !defined(TARGET_MIPS64)
/* MXU accumulate add/subtract 1-bit pattern 'aptn1' */
@ -27400,6 +27427,9 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx)
}
}
#if defined(TARGET_MIPS64)
static void decode_mmi0(CPUMIPSState *env, DisasContext *ctx)
{
uint32_t opc = MASK_MMI0(ctx->opcode);
@ -27644,6 +27674,8 @@ static void decode_mmi_sq(CPUMIPSState *env, DisasContext *ctx)
gen_mmi_sq(ctx, base, rt, offset);
}
#endif
static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx)
{
TCGContext *tcg_ctx = env->uc->tcg_ctx;
@ -28982,10 +29014,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat
decode_opc_special(env, ctx);
break;
case OPC_SPECIAL2:
#if defined(TARGET_MIPS64)
if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) {
decode_mmi(env, ctx);
#if !defined(TARGET_MIPS64)
} else if (ctx->insn_flags & ASE_MXU) {
#else
if (ctx->insn_flags & ASE_MXU) {
decode_opc_mxu(env, ctx);
#endif
} else {
@ -28993,11 +29026,15 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat
}
break;
case OPC_SPECIAL3:
#if defined(TARGET_MIPS64)
if (ctx->insn_flags & INSN_R5900) {
decode_mmi_sq(env, ctx); /* MMI_OPC_SQ */
} else {
decode_opc_special3(env, ctx);
}
#else
decode_opc_special3(env, ctx);
#endif
break;
case OPC_REGIMM:
op1 = MASK_REGIMM(ctx->opcode);
@ -29667,7 +29704,9 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx, bool *insn_need_pat
break;
case OPC_MSA: /* OPC_MDMX */
if (ctx->insn_flags & INSN_R5900) {
#if defined(TARGET_MIPS64)
decode_mmi_lq(env, ctx); /* MMI_OPC_LQ */
#endif
} else {
/* MDMX: Not implemented. */
gen_msa(env, ctx);