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target/arm: Enforce FP access to FPCR/FPSR

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Backports commit fe03d45f9e9baa89e8c4da50de771767d5d48990 from qemu
This commit is contained in:
Richard Henderson 2018-03-08 09:05:52 -05:00 committed by Lioncash
parent 1bff556dbc
commit d5c4d3e3c3
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GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 25 additions and 21 deletions
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35
qemu/target/arm/cpu.h
View file

@ -1680,7 +1680,7 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
}
/* ARMCPRegInfo type field bits. If the SPECIAL bit is set this is a
* special-behaviour cp reg and bits [15..8] indicate what behaviour
* special-behaviour cp reg and bits [11..8] indicate what behaviour
* it has. Otherwise it is a simple cp reg, where CONST indicates that
* TCG can assume the value to be constant (ie load at translate time)
* and 64BIT indicates a 64 bit wide coprocessor register. SUPPRESS_TB_END
@ -1701,24 +1701,25 @@ static inline uint64_t cpreg_to_kvm_id(uint32_t cpregid)
* need to be surrounded by gen_io_start()/gen_io_end(). In particular,
* registers which implement clocks or timers require this.
*/
#define ARM_CP_SPECIAL 1
#define ARM_CP_CONST 2
#define ARM_CP_64BIT 4
#define ARM_CP_SUPPRESS_TB_END 8
#define ARM_CP_OVERRIDE 16
#define ARM_CP_ALIAS 32
#define ARM_CP_IO 64
#define ARM_CP_NO_RAW 128
#define ARM_CP_NOP (ARM_CP_SPECIAL | (1 << 8))
#define ARM_CP_WFI (ARM_CP_SPECIAL | (2 << 8))
#define ARM_CP_NZCV (ARM_CP_SPECIAL | (3 << 8))
#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | (4 << 8))
#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | (5 << 8))
#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
#define ARM_CP_SPECIAL 0x0001
#define ARM_CP_CONST 0x0002
#define ARM_CP_64BIT 0x0004
#define ARM_CP_SUPPRESS_TB_END 0x0008
#define ARM_CP_OVERRIDE 0x0010
#define ARM_CP_ALIAS 0x0020
#define ARM_CP_IO 0x0040
#define ARM_CP_NO_RAW 0x0080
#define ARM_CP_NOP (ARM_CP_SPECIAL | 0x0100)
#define ARM_CP_WFI (ARM_CP_SPECIAL | 0x0200)
#define ARM_CP_NZCV (ARM_CP_SPECIAL | 0x0300)
#define ARM_CP_CURRENTEL (ARM_CP_SPECIAL | 0x0400)
#define ARM_CP_DC_ZVA (ARM_CP_SPECIAL | 0x0500)
#define ARM_LAST_SPECIAL ARM_CP_DC_ZVA
#define ARM_CP_FPU 0x1000
/* Used only as a terminator for ARMCPRegInfo lists */
#define ARM_CP_SENTINEL 0xffff
#define ARM_CP_SENTINEL 0xffff
/* Mask of only the flag bits in a type field */
#define ARM_CP_FLAG_MASK 0xff
#define ARM_CP_FLAG_MASK 0x10ff
/* Valid values for ARMCPRegInfo state field, indicating which of
* the AArch32 and AArch64 execution states this register is visible in.

8
qemu/target/arm/helper.c
View file

@ -3064,11 +3064,11 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
{ "DAIF", 0,4,2, 3,3,1, ARM_CP_STATE_AA64,
ARM_CP_NO_RAW, PL0_RW, 0, NULL, 0, offsetof(CPUARMState, daif), {0, 0},
aa64_daif_access, NULL, aa64_daif_write, NULL,NULL, arm_cp_reset_ignore },
{ "FPCR", 0,4,4, 3,3,0, ARM_CP_STATE_AA64,
0, PL0_RW, 0, NULL, 0, 0, {0, 0},
{ "FPCR", 0,4,4, 3,3,0, ARM_CP_STATE_AA64, ARM_CP_FPU,
PL0_RW, 0, NULL, 0, 0, {0, 0},
NULL, aa64_fpcr_read, aa64_fpcr_write },
{ "FPSR", 0,4,4, 3,3,1, ARM_CP_STATE_AA64,
0, PL0_RW, 0, NULL, 0, 0, {0, 0},
{ "FPSR", 0,4,4, 3,3,1, ARM_CP_STATE_AA64, ARM_CP_FPU,
PL0_RW, 0, NULL, 0, 0, {0, 0},
NULL, aa64_fpsr_read, aa64_fpsr_write },
{ "DCZID_EL0", 0,0,0, 3,3,7, ARM_CP_STATE_AA64,
ARM_CP_NO_RAW, PL0_R, 0, NULL, 0, 0, {0, 0},

3
qemu/target/arm/translate-a64.c
View file

@ -1690,6 +1690,9 @@ static void handle_sys(DisasContext *s, uint32_t insn, bool isread,
default:
break;
}
if ((ri->type & ARM_CP_FPU) && !fp_access_check(s)) {
return;
}
// Unicorn: if'd out
#if 0