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target/riscv: fix rsub gvec tcg_assert_listed_vecop assertion

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gvec should provide vecop_list to avoid:
"tcg_tcg_assert_listed_vecop: code should not be reached bug" assertion.

Backports 7acafcfa844fd93f5ff073077007627338bd6739
This commit is contained in:
Frank Chang 2021-03-08 12:11:00 -05:00 committed by Lioncash
parent 798ce750d5
commit d75c8e7fcf
1 changed files with 5 additions and 0 deletions
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5
qemu/target/riscv/insn_trans/trans_rvv.inc.c
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@ -971,22 +971,27 @@ static void gen_rsub_vec(TCGContext *s, unsigned vece, TCGv_vec r, TCGv_vec a, T
static void tcg_gen_gvec_rsubs(TCGContext *s, unsigned vece, uint32_t dofs, uint32_t aofs,
TCGv_i64 c, uint32_t oprsz, uint32_t maxsz)
{
static const TCGOpcode vecop_list[] = { INDEX_op_sub_vec, 0 };
static const GVecGen2s rsub_op[4] = {
{ .fni8 = gen_vec_rsub8_i64,
.fniv = gen_rsub_vec,
.fno = gen_helper_vec_rsubs8,
.opt_opc = vecop_list,
.vece = MO_8 },
{ .fni8 = gen_vec_rsub16_i64,
.fniv = gen_rsub_vec,
.fno = gen_helper_vec_rsubs16,
.opt_opc = vecop_list,
.vece = MO_16 },
{ .fni4 = gen_rsub_i32,
.fniv = gen_rsub_vec,
.fno = gen_helper_vec_rsubs32,
.opt_opc = vecop_list,
.vece = MO_32 },
{ .fni8 = gen_rsub_i64,
.fniv = gen_rsub_vec,
.fno = gen_helper_vec_rsubs64,
.opt_opc = vecop_list,
.prefer_i64 = TCG_TARGET_REG_BITS == 64,
.vece = MO_64 },
};