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target/arm: Improve masking of SCR RES0 bits

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Protect reads of aa64 id registers with ARM_CP_STATE_AA64.
Use this as a simpler test than arm_el_is_aa64, since EL3
cannot change mode.

Backports commit 252e8c69669599b4bcff802df300726300292f47 from qemu
This commit is contained in:
Richard Henderson 2021-02-25 13:56:33 -05:00 committed by Lioncash
parent 1a35600453
commit d81feac642
1 changed files with 8 additions and 1 deletions
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9
qemu/target/arm/helper.c
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@ -1707,9 +1707,16 @@ static void scr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
uint32_t valid_mask = 0x3fff; uint32_t valid_mask = 0x3fff;
ARMCPU *cpu = env_archcpu(env); ARMCPU *cpu = env_archcpu(env);
if (arm_el_is_aa64(env, 3)) { if (ri->state == ARM_CP_STATE_AA64) {
value |= SCR_FW | SCR_AW; /* these two bits are RES1. */ value |= SCR_FW | SCR_AW; /* these two bits are RES1. */
valid_mask &= ~SCR_NET; valid_mask &= ~SCR_NET;
if (cpu_isar_feature(aa64_lor, cpu)) {
valid_mask |= SCR_TLOR;
}
if (cpu_isar_feature(aa64_pauth, cpu)) {
valid_mask |= SCR_API | SCR_APK;
}
} else { } else {
valid_mask &= ~(SCR_RW | SCR_ST); valid_mask &= ~(SCR_RW | SCR_ST);
} }