mirror of
https://github.com/yuzu-emu/unicorn.git
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del qemu/include/hw/irq.h
This commit is contained in:
Nguyen Anh Quynh
parent
0640b35943
commit
d836ec62fc
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@ -12,16 +12,10 @@
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#define ARM_MISC_H 1
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#include "exec/memory.h"
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#include "hw/irq.h"
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void tosa_machine_init(struct uc_struct *uc);
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void machvirt_machine_init(struct uc_struct *uc); // ARM64
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/* armv7m.c */
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qemu_irq *armv7m_init(MemoryRegion *system_memory,
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int flash_size, int sram_size,
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const char *kernel_filename, const char *cpu_model);
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/* arm_boot.c */
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struct arm_boot_info {
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uint64_t ram_size;
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@ -9,7 +9,6 @@
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#endif
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#include "exec/ioport.h"
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#include "hw/irq.h"
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#include "qemu/log.h"
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#ifdef NEED_CPU_H
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@ -1,64 +0,0 @@
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#ifndef QEMU_IRQ_H
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#define QEMU_IRQ_H
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/* Generic IRQ/GPIO pin infrastructure. */
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#define TYPE_IRQ "irq"
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typedef struct IRQState *qemu_irq;
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typedef void (*qemu_irq_handler)(void *opaque, int n, int level);
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void qemu_set_irq(qemu_irq irq, int level);
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static inline void qemu_irq_raise(qemu_irq irq)
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{
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}
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static inline void qemu_irq_lower(qemu_irq irq)
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{
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qemu_set_irq(irq, 0);
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}
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static inline void qemu_irq_pulse(qemu_irq irq)
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{
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qemu_set_irq(irq, 1);
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qemu_set_irq(irq, 0);
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}
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/* Returns an array of N IRQs. Each IRQ is assigned the argument handler and
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* opaque data.
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*/
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qemu_irq *qemu_allocate_irqs(qemu_irq_handler handler, void *opaque, int n);
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/*
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* Allocates a single IRQ. The irq is assigned with a handler, an opaque
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* data and the interrupt number.
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*/
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qemu_irq qemu_allocate_irq(qemu_irq_handler handler, void *opaque, int n);
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/* Extends an Array of IRQs. Old IRQs have their handlers and opaque data
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* preserved. New IRQs are assigned the argument handler and opaque data.
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*/
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qemu_irq *qemu_extend_irqs(qemu_irq *old, int n_old, qemu_irq_handler handler,
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void *opaque, int n);
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void qemu_free_irqs(qemu_irq *s, int n);
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void qemu_free_irq(qemu_irq irq);
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/* Returns a new IRQ with opposite polarity. */
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qemu_irq qemu_irq_invert(qemu_irq irq);
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/* Returns a new IRQ which feeds into both the passed IRQs */
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qemu_irq qemu_irq_split(qemu_irq irq1, qemu_irq irq2);
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/* Returns a new IRQ set which connects 1:1 to another IRQ set, which
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* may be set later.
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*/
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qemu_irq *qemu_irq_proxy(qemu_irq **target, int n);
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/* For internal use in qtest. Similar to qemu_irq_split, but operating
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on an existing vector of qemu_irq. */
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void qemu_irq_intercept_in(qemu_irq *gpio_in, qemu_irq_handler handler, int n);
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#endif
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@ -7,28 +7,6 @@
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#include "exec/memory.h"
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/* gt64xxx.c */
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PCIBus *gt64120_register(qemu_irq *pic);
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/* bonito.c */
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PCIBus *bonito_init(qemu_irq *pic);
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/* rc4030.c */
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typedef struct rc4030DMAState *rc4030_dma;
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void rc4030_dma_memory_rw(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write);
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void rc4030_dma_read(void *dma, uint8_t *buf, int len);
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void rc4030_dma_write(void *dma, uint8_t *buf, int len);
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void *rc4030_init(qemu_irq timer, qemu_irq jazz_bus,
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qemu_irq **irqs, rc4030_dma **dmas,
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MemoryRegion *sysmem);
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/* dp8393x.c */
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void dp83932_init(NICInfo *nd, hwaddr base, int it_shift,
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MemoryRegion *address_space,
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qemu_irq irq, void* mem_opaque,
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void (*memory_rw)(void *opaque, hwaddr addr, uint8_t *buf, int len, int is_write));
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void mips_machine_init(struct uc_struct *uc);
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void mips_cpu_register_types(void *opaque);
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@ -5,7 +5,6 @@
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#include "qemu/typedefs.h"
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#include "qemu/bitmap.h"
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#include "qom/object.h"
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#include "hw/irq.h"
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#include "qapi/error.h"
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enum {
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@ -132,7 +131,6 @@ typedef struct NamedGPIOList NamedGPIOList;
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struct NamedGPIOList {
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char *name;
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qemu_irq *in;
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int num_in;
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int num_out;
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QLIST_ENTRY(NamedGPIOList) node;
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@ -260,29 +258,12 @@ void qdev_unplug(DeviceState *dev, Error **errp);
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void qdev_machine_creation_done(void);
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bool qdev_machine_modified(void);
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qemu_irq qdev_get_gpio_in(DeviceState *dev, int n);
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qemu_irq qdev_get_gpio_in_named(DeviceState *dev, const char *name, int n);
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void qdev_connect_gpio_out(DeviceState *dev, int n, qemu_irq pin);
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void qdev_connect_gpio_out_named(DeviceState *dev, const char *name, int n,
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qemu_irq pin);
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qemu_irq qdev_get_gpio_out_connector(DeviceState *dev, const char *name, int n);
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qemu_irq qdev_intercept_gpio_out(DeviceState *dev, qemu_irq icpt,
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const char *name, int n);
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BusState *qdev_get_child_bus(DeviceState *dev, const char *name);
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/*** Device API. ***/
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/* Register device properties. */
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/* GPIO inputs also double as IRQ sinks. */
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void qdev_init_gpio_in(DeviceState *dev, qemu_irq_handler handler, int n);
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void qdev_init_gpio_out(DeviceState *dev, qemu_irq *pins, int n);
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void qdev_init_gpio_in_named(DeviceState *dev, qemu_irq_handler handler,
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const char *name, int n);
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void qdev_init_gpio_out_named(DeviceState *dev, qemu_irq *pins,
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const char *name, int n);
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void qdev_pass_gpios(DeviceState *dev, DeviceState *container,
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const char *name);
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