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target/arm: fix stage 2 page-walks in 32-bit emulation

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Using a target unsigned long would limit the Input Address to a LPAE
page-walk to 32 bits on AArch32 and 64 bits on AArch64. This is okay
for stage 1 or on AArch64, but it is insufficient for stage 2 on
AArch32. In that later case, the Input Address can have up to 40 bits.

Backports commit 98e8779770c40901ed585745aacc9a8e2b934a28
This commit is contained in:
Rémi Denis-Courmont 2021-03-02 13:36:55 -05:00 committed by Lioncash
parent 5eb86e4d3c
commit d9592046ef
1 changed files with 2 additions and 2 deletions
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4
qemu/target/arm/helper.c
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@ -27,7 +27,7 @@
#ifndef CONFIG_USER_ONLY
static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
bool s1_is_el0,
hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,
@ -10715,7 +10715,7 @@ static ARMVAParameters aa32_va_parameters(CPUARMState *env, uint32_t va,
* @fi: set to fault info if the translation fails
* @cacheattrs: (if non-NULL) set to the cacheability/shareability attributes
*/
static bool get_phys_addr_lpae(CPUARMState *env, target_ulong address,
static bool get_phys_addr_lpae(CPUARMState *env, uint64_t address,
MMUAccessType access_type, ARMMMUIdx mmu_idx,
bool s1_is_el0,
hwaddr *phys_ptr, MemTxAttrs *txattrs, int *prot,