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target/mips: Add a comment with an overview of CP0 registers

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Add a comment with an overview of CP0 registers close to the
definition of their corresponding fields in CPUMIPSState.

Backports commit a86d421e18d58b32d6eaba1e79160e2b4e5a0a6c from qemu
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Aleksandar Markovic 2018-10-23 13:06:28 -04:00 committed by Lioncash
parent 5f12065284
commit d9ae47e2da
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1 changed files with 109 additions and 0 deletions
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109
qemu/target/mips/cpu.h
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@ -196,6 +196,115 @@ struct CPUMIPSState {
#define MSAIR_ProcID 8 #define MSAIR_ProcID 8
#define MSAIR_Rev 0 #define MSAIR_Rev 0
/*
* Summary of CP0 registers
* ========================
*
*
* Register 0 Register 1 Register 2 Register 3
* ---------- ---------- ---------- ----------
*
* 0 Index Random EntryLo0 EntryLo1
* 1 MVPControl VPEControl TCStatus GlobalNumber
* 2 MVPConf0 VPEConf0 TCBind
* 3 MVPConf1 VPEConf1 TCRestart
* 4 VPControl YQMask TCHalt
* 5 VPESchedule TCContext
* 6 VPEScheFBack TCSchedule
* 7 VPEOpt TCScheFBack TCOpt
*
*
* Register 4 Register 5 Register 6 Register 7
* ---------- ---------- ---------- ----------
*
* 0 Context PageMask Wired HWREna
* 1 ContextConfig PageGrain SRSConf0
* 2 UserLocal SegCtl0 SRSConf1
* 3 XContextConfig SegCtl1 SRSConf2
* 4 DebugContextID SegCtl2 SRSConf3
* 5 MemoryMapID PWBase SRSConf4
* 6 PWField PWCtl
* 7 PWSize
*
*
* Register 8 Register 9 Register 10 Register 11
* ---------- ---------- ----------- -----------
*
* 0 BadVAddr Count EntryHi Compare
* 1 BadInstr
* 2 BadInstrP
* 3 BadInstrX
* 4 GuestCtl1 GuestCtl0Ext
* 5 GuestCtl2
* 6 GuestCtl3
* 7
*
*
* Register 12 Register 13 Register 14 Register 15
* ----------- ----------- ----------- -----------
*
* 0 Status Cause EPC PRId
* 1 IntCtl EBase
* 2 SRSCtl NestedEPC CDMMBase
* 3 SRSMap CMGCRBase
* 4 View_IPL View_RIPL BEVVA
* 5 SRSMap2 NestedExc
* 6 GuestCtl0
* 7 GTOffset
*
*
* Register 16 Register 17 Register 18 Register 19
* ----------- ----------- ----------- -----------
*
* 0 Config LLAddr WatchLo WatchHi
* 1 Config1 MAAR WatchLo WatchHi
* 2 Config2 MAARI WatchLo WatchHi
* 3 Config3 WatchLo WatchHi
* 4 Config4 WatchLo WatchHi
* 5 Config5 WatchLo WatchHi
* 6 WatchLo WatchHi
* 7 WatchLo WatchHi
*
*
* Register 20 Register 21 Register 22 Register 23
* ----------- ----------- ----------- -----------
*
* 0 XContext Debug
* 1 TraceControl
* 2 TraceControl2
* 3 UserTraceData1
* 4 TraceIBPC
* 5 TraceDBPC
* 6 Debug2
* 7
*
*
* Register 24 Register 25 Register 26 Register 27
* ----------- ----------- ----------- -----------
*
* 0 DEPC PerfCnt ErrCtl CacheErr
* 1 PerfCnt
* 2 TraceControl3 PerfCnt
* 3 UserTraceData2 PerfCnt
* 4 PerfCnt
* 5 PerfCnt
* 6 PerfCnt
* 7 PerfCnt
*
*
* Register 28 Register 29 Register 30 Register 31
* ----------- ----------- ----------- -----------
*
* 0 DataLo DataHi ErrorEPC DESAVE
* 1 TagLo TagHi
* 2 DataLo DataHi KScratch<n>
* 3 TagLo TagHi KScratch<n>
* 4 DataLo DataHi KScratch<n>
* 5 TagLo TagHi KScratch<n>
* 6 DataLo DataHi KScratch<n>
* 7 TagLo TagHi KScratch<n>
*
*/
int32_t CP0_Index; int32_t CP0_Index;
/* CP0_MVP* are per MVP registers. */ /* CP0_MVP* are per MVP registers. */
int32_t CP0_VPControl; int32_t CP0_VPControl;