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https://github.com/yuzu-emu/unicorn.git
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target/mips: Add emulation of MXU instruction D16MUL
Backports commit 72c9bcf89c59ee1a8e4545069de3efcbeb4d4833 from qemu
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cad0283888
commit
db2e8c1761
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@ -24325,6 +24325,69 @@ static void gen_mxu_s8ldd(DisasContext *ctx)
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tcg_temp_free(tcg_ctx, t1);
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}
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/*
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* D16MUL XRa, XRb, XRc, XRd, optn2 - Signed 16 bit pattern multiplication
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*/
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static void gen_mxu_d16mul(DisasContext *ctx)
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{
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TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
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TCGv t0, t1, t2, t3;
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TCGLabel *l0;
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uint32_t XRa, XRb, XRc, XRd, optn2;
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t0 = tcg_temp_new(tcg_ctx);
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t1 = tcg_temp_new(tcg_ctx);
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t2 = tcg_temp_new(tcg_ctx);
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t3 = tcg_temp_new(tcg_ctx);
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l0 = gen_new_label(tcg_ctx);
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XRa = extract32(ctx->opcode, 6, 4);
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XRb = extract32(ctx->opcode, 10, 4);
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XRc = extract32(ctx->opcode, 14, 4);
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XRd = extract32(ctx->opcode, 18, 4);
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optn2 = extract32(ctx->opcode, 22, 2);
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gen_load_mxu_cr(ctx, t0);
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tcg_gen_andi_tl(tcg_ctx, t0, t0, MXU_CR_MXU_EN);
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tcg_gen_brcondi_tl(tcg_ctx, TCG_COND_NE, t0, MXU_CR_MXU_EN, l0);
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gen_load_mxu_gpr(ctx, t1, XRb);
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tcg_gen_sextract_tl(tcg_ctx, t0, t1, 0, 16);
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tcg_gen_sextract_tl(tcg_ctx, t1, t1, 16, 16);
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gen_load_mxu_gpr(ctx, t3, XRc);
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tcg_gen_sextract_tl(tcg_ctx, t2, t3, 0, 16);
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tcg_gen_sextract_tl(tcg_ctx, t3, t3, 16, 16);
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switch (optn2) {
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case MXU_OPTN2_WW: /* XRB.H*XRC.H == lop, XRB.L*XRC.L == rop */
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tcg_gen_mul_tl(tcg_ctx, t3, t1, t3);
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tcg_gen_mul_tl(tcg_ctx, t2, t0, t2);
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break;
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case MXU_OPTN2_LW: /* XRB.L*XRC.H == lop, XRB.L*XRC.L == rop */
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tcg_gen_mul_tl(tcg_ctx, t3, t0, t3);
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tcg_gen_mul_tl(tcg_ctx, t2, t0, t2);
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break;
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case MXU_OPTN2_HW: /* XRB.H*XRC.H == lop, XRB.H*XRC.L == rop */
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tcg_gen_mul_tl(tcg_ctx, t3, t1, t3);
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tcg_gen_mul_tl(tcg_ctx, t2, t1, t2);
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break;
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case MXU_OPTN2_XW: /* XRB.L*XRC.H == lop, XRB.H*XRC.L == rop */
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tcg_gen_mul_tl(tcg_ctx, t3, t0, t3);
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tcg_gen_mul_tl(tcg_ctx, t2, t1, t2);
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break;
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}
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gen_store_mxu_gpr(ctx, t3, XRa);
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gen_store_mxu_gpr(ctx, t2, XRd);
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gen_set_label(tcg_ctx, l0);
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tcg_temp_free(tcg_ctx, t0);
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tcg_temp_free(tcg_ctx, t1);
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tcg_temp_free(tcg_ctx, t2);
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tcg_temp_free(tcg_ctx, t3);
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}
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/*
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* Decoding engine for MXU
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@ -25289,9 +25352,7 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx)
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decode_opc_mxu__pool02(env, ctx);
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break;
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case OPC_MXU_D16MUL:
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/* TODO: Implement emulation of D16MUL instruction. */
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MIPS_INVAL("OPC_MXU_D16MUL");
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generate_exception_end(ctx, EXCP_RI);
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gen_mxu_d16mul(ctx);
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break;
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case OPC_MXU__POOL03:
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decode_opc_mxu__pool03(env, ctx);
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