yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2024-12-23 00:05:36 +00:00
Code Issues Packages Projects Releases Wiki Activity

target/riscv: Fix the interrupt cause code

Browse source 
Backports 84b1c04bbaf48798a535b38410a0bf839f4a1943
This commit is contained in:
Alistair Francis 2021-03-08 13:28:09 -05:00 committed by Lioncash
parent a5311a267d
commit db749a279d
1 changed files with 3 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

5
qemu/target/riscv/cpu_helper.c
View file

@ -919,14 +919,15 @@ void riscv_cpu_do_interrupt(CPUState *cs)
if (riscv_cpu_virt_enabled(env) && ((hdeleg >> cause) & 1) &&
!force_hs_execp) {
/* Trap to VS mode */
/*
* See if we need to adjust cause. Yes if its VS mode interrupt
* no if hypervisor has delegated one of hs mode's interrupt
*/
if (cause == IRQ_VS_TIMER || cause == IRQ_VS_SOFT ||
cause == IRQ_VS_EXT)
cause == IRQ_VS_EXT) {
cause = cause - 1;
/* Trap to VS mode */
}
env->hstatus = set_field(env->hstatus, HSTATUS_GVA, 0);
} else if (riscv_cpu_virt_enabled(env)) {
/* Trap into HS mode, from virt */