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target/mips: Implement CP0 Config1.WR bit functionality

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Add testing Config1.WR bit into watch exception handling logic.

Backports commit fa192d4974de3ace960d03803ab9d2f09abd9282 from qemu
This commit is contained in:
Stefan Markovic 2018-08-17 14:23:34 -04:00 committed by Lioncash
parent 4b6a9ce61b
commit dbebd7f27f
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 8 additions and 0 deletions
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8
qemu/target/mips/translate.c
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@ -5594,6 +5594,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(tcg_ctx, mfc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@ -5611,6 +5612,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(tcg_ctx, mfc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@ -6291,6 +6293,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(tcg_ctx, mtc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@ -6308,6 +6311,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(tcg_ctx, mtc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@ -6989,6 +6993,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(tcg_ctx, dmfc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@ -7006,6 +7011,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_1e0i(tcg_ctx, mfc0_watchhi, arg, sel);
rn = "WatchHi";
break;
@ -7668,6 +7674,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(tcg_ctx, mtc0_watchlo, arg, sel);
rn = "WatchLo";
break;
@ -7685,6 +7692,7 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
case 5:
case 6:
case 7:
CP0_CHECK(ctx->CP0_Config1 & (1 << CP0C1_WR));
gen_helper_0e1i(tcg_ctx, mtc0_watchhi, arg, sel);
rn = "WatchHi";
break;