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target/arm: Only implement doubles if the FPU supports them

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The architecture permits FPUs which have only single-precision
support, not double-precision; Cortex-M4 and Cortex-M33 are
both like that. Add the necessary checks on the MVFR0 FPDP
field so that we UNDEF any double-precision instructions on
CPUs like this.

Note that even if FPDP==0 the insns like VMOV-to/from-gpreg,
VLDM/VSTM, VLDR/VSTR which take double precision registers
still exist.

Backports commit 1120827fa182f0e76226df7ffe7a86598d1df54f from qemu
This commit is contained in:
Peter Maydell 2019-06-25 18:55:23 -05:00 committed by Lioncash
parent cfac686c95
commit dc1f2247ec
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 90 additions and 0 deletions
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6
qemu/target/arm/cpu.h
View file

@ -3339,6 +3339,12 @@ static inline bool isar_feature_aa32_fpshvec(const ARMISARegisters *id)
return FIELD_EX64(id->mvfr0, MVFR0, FPSHVEC) > 0;
}
static inline bool isar_feature_aa32_fpdp(const ARMISARegisters *id)
{
/* Return true if CPU supports double precision floating point */
return FIELD_EX64(id->mvfr0, MVFR0, FPDP) > 0;
}
/*
* We always set the FP and SIMD FP16 fields to indicate identical
* levels of support (assuming SIMD is implemented at all), so

84
qemu/target/arm/translate-vfp.inc.c
View file

@ -209,6 +209,11 @@ static bool trans_VSEL(DisasContext *s, arg_VSEL *a)
((a->vm | a->vn | a->vd) & 0x10)) {
return false;
}
if (dp && !dc_isar_feature(aa32_fpdp, s)) {
return false;
}
rd = a->vd;
rn = a->vn;
rm = a->vm;
@ -338,6 +343,11 @@ static bool trans_VMINMAXNM(DisasContext *s, arg_VMINMAXNM *a)
((a->vm | a->vn | a->vd) & 0x10)) {
return false;
}
if (dp && !dc_isar_feature(aa32_fpdp, s)) {
return false;
}
rd = a->vd;
rn = a->vn;
rm = a->vm;
@ -420,6 +430,11 @@ static bool trans_VRINT(DisasContext *s, arg_VRINT *a)
((a->vm | a->vd) & 0x10)) {
return false;
}
if (dp && !dc_isar_feature(aa32_fpdp, s)) {
return false;
}
rd = a->vd;
rm = a->vm;
@ -479,6 +494,11 @@ static bool trans_VCVT(DisasContext *s, arg_VCVT *a)
if (dp && !dc_isar_feature(aa32_fp_d32, s) && (a->vm & 0x10)) {
return false;
}
if (dp && !dc_isar_feature(aa32_fpdp, s)) {
return false;
}
rd = a->vd;
rm = a->vm;
@ -1320,6 +1340,10 @@ static bool do_vfp_3op_dp(DisasContext *s, VFPGen3OpDPFn *fn,
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!dc_isar_feature(aa32_fpshvec, s) &&
(veclen != 0 || s->vec_stride != 0)) {
return false;
@ -1472,6 +1496,10 @@ static bool do_vfp_2op_dp(DisasContext *s, VFPGen2OpDPFn *fn, int vd, int vm)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -1765,6 +1793,10 @@ static bool trans_VFM_sp(DisasContext *s, arg_VFM_sp *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -1926,6 +1958,10 @@ static bool trans_VMOV_imm_dp(DisasContext *s, arg_VMOV_imm_dp *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!dc_isar_feature(aa32_fpshvec, s) &&
(veclen != 0 || s->vec_stride != 0)) {
return false;
@ -2068,6 +2104,10 @@ static bool trans_VCMP_dp(DisasContext *s, arg_VCMP_dp *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -2139,6 +2179,10 @@ static bool trans_VCVT_f64_f16(DisasContext *s, arg_VCVT_f64_f16 *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -2203,6 +2247,10 @@ static bool trans_VCVT_f16_f64(DisasContext *s, arg_VCVT_f16_f64 *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -2261,6 +2309,10 @@ static bool trans_VRINTR_dp(DisasContext *s, arg_VRINTR_dp *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -2320,6 +2372,10 @@ static bool trans_VRINTZ_dp(DisasContext *s, arg_VRINTZ_dp *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -2377,6 +2433,10 @@ static bool trans_VRINTX_dp(DisasContext *s, arg_VRINTX_dp *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -2402,6 +2462,10 @@ static bool trans_VCVT_sp(DisasContext *s, arg_VCVT_sp *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -2427,6 +2491,10 @@ static bool trans_VCVT_dp(DisasContext *s, arg_VCVT_dp *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -2479,6 +2547,10 @@ static bool trans_VCVT_int_dp(DisasContext *s, arg_VCVT_int_dp *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -2516,6 +2588,10 @@ static bool trans_VJCVT(DisasContext *s, arg_VJCVT *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -2607,6 +2683,10 @@ static bool trans_VCVT_fix_dp(DisasContext *s, arg_VCVT_fix_dp *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
@ -2701,6 +2781,10 @@ static bool trans_VCVT_dp_int(DisasContext *s, arg_VCVT_dp_int *a)
return false;
}
if (!dc_isar_feature(aa32_fpdp, s)) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}