yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-02-25 11:46:58 +00:00
Code Issues Packages Projects Releases Wiki Activity

arm: Don't decode MRS(banked) or MSR(banked) for M profile

Browse source 
M profile doesn't have the MSR(banked) and MRS(banked) instructions
and uses the encodings for different kinds of M-profile MRS/MSR.
Guard the relevant bits of the decode logic to make sure we don't
accidentally fall into them by accident on M-profile.

(The bit being checked for this (bit 5) is part of the SYSm field on
M-profile, but since no currently allocated system registers have
encodings with bit 5 of SYSm set, this hasn't been a problem in
practice.)

Backports commit 43ac65742319ef5ac4461daf43316b189cd21e89 from qemu
This commit is contained in:
Peter Maydell 2018-03-02 13:08:18 -05:00 committed by Lioncash
parent cc2a6a2728
commit dc44eded51
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 4 additions and 2 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

6
qemu/target/arm/translate.c
View file

@ -10650,7 +10650,8 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
gen_exception_return(s, tmp);
break;
case 6: /* MRS */
if (extract32(insn, 5, 1)) {
if (extract32(insn, 5, 1) &&
!arm_dc_feature(s, ARM_FEATURE_M)) {
/* MRS (banked) */
int sysm = extract32(insn, 16, 4) |
(extract32(insn, 4, 1) << 4);
@ -10671,7 +10672,8 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
store_reg(s, rd, tmp);
break;
case 7: /* MRS */
if (extract32(insn, 5, 1)) {
if (extract32(insn, 5, 1) &&
!arm_dc_feature(s, ARM_FEATURE_M)) {
/* MRS (banked) */
int sysm = extract32(insn, 16, 4) |
(extract32(insn, 4, 1) << 4);