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target/riscv: Remove user version information

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Remove the user version information. This was never used and never
publically exposed in a release of QEMU, so let's just remove it. In
future to manage versions we can extend the extension properties to
specify version.

Backports commit c9a73910c34a2147bcf6a3b5194d27abb19c2e54 from qemu
This commit is contained in:
Alistair Francis 2020-04-30 21:06:47 -04:00 committed by Lioncash
parent 15e558e9cc
commit dc7cbbe2c1
2 changed files with 8 additions and 11 deletions
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17
qemu/target/riscv/cpu.c
View file

@ -93,9 +93,8 @@ static void set_misa(CPURISCVState *env, target_ulong misa)
env->misa_mask = env->misa = misa;
}
static void set_versions(CPURISCVState *env, int user_ver, int priv_ver)
static void set_priv_version(CPURISCVState *env, int priv_ver)
{
env->user_ver = user_ver;
env->priv_ver = priv_ver;
}
@ -115,7 +114,7 @@ static void riscv_any_cpu_init(struct uc_struct *uc, Object *obj, void *opaque)
{
CPURISCVState *env = &RISCV_CPU(uc, obj)->env;
set_misa(env, RVXLEN | RVI | RVM | RVA | RVF | RVD | RVC | RVU);
set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_11_0);
set_priv_version(env, PRIV_VERSION_1_11_0);
set_resetvec(env, DEFAULT_RSTVEC);
}
@ -131,7 +130,7 @@ static void rv32gcsu_priv1_09_1_cpu_init(struct uc_struct *uc, Object *obj, void
{
CPURISCVState *env = &RISCV_CPU(uc, obj)->env;
set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_09_1);
set_priv_version(env, PRIV_VERSION_1_09_1);
set_resetvec(env, DEFAULT_RSTVEC);
set_feature(env, RISCV_FEATURE_MMU);
set_feature(env, RISCV_FEATURE_PMP);
@ -141,7 +140,7 @@ static void rv32gcsu_priv1_10_0_cpu_init(struct uc_struct *uc, Object *obj, void
{
CPURISCVState *env = &RISCV_CPU(uc, obj)->env;
set_misa(env, RV32 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
set_priv_version(env, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
set_feature(env, RISCV_FEATURE_MMU);
set_feature(env, RISCV_FEATURE_PMP);
@ -151,7 +150,7 @@ static void rv32imacu_nommu_cpu_init(struct uc_struct *uc, Object *obj, void *op
{
CPURISCVState *env = &RISCV_CPU(uc, obj)->env;
set_misa(env, RV32 | RVI | RVM | RVA | RVC | RVU);
set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
set_priv_version(env, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
set_feature(env, RISCV_FEATURE_PMP);
}
@ -168,7 +167,7 @@ static void rv64gcsu_priv1_09_1_cpu_init(struct uc_struct *uc, Object *obj, void
{
CPURISCVState *env = &RISCV_CPU(uc, obj)->env;
set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_09_1);
set_priv_version(env, PRIV_VERSION_1_09_1);
set_resetvec(env, DEFAULT_RSTVEC);
set_feature(env, RISCV_FEATURE_MMU);
set_feature(env, RISCV_FEATURE_PMP);
@ -178,7 +177,7 @@ static void rv64gcsu_priv1_10_0_cpu_init(struct uc_struct *uc, Object *obj, void
{
CPURISCVState *env = &RISCV_CPU(uc, obj)->env;
set_misa(env, RV64 | RVI | RVM | RVA | RVF | RVD | RVC | RVS | RVU);
set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
set_priv_version(env, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
set_feature(env, RISCV_FEATURE_MMU);
set_feature(env, RISCV_FEATURE_PMP);
@ -188,7 +187,7 @@ static void rv64imacu_nommu_cpu_init(struct uc_struct *uc, Object *obj, void *op
{
CPURISCVState *env = &RISCV_CPU(uc, obj)->env;
set_misa(env, RV64 | RVI | RVM | RVA | RVC | RVU);
set_versions(env, USER_VERSION_2_02_0, PRIV_VERSION_1_10_0);
set_priv_version(env, PRIV_VERSION_1_10_0);
set_resetvec(env, DEFAULT_RSTVEC);
set_feature(env, RISCV_FEATURE_PMP);
}

2
qemu/target/riscv/cpu.h
View file

@ -83,7 +83,6 @@ enum {
RISCV_FEATURE_MISA
};
#define USER_VERSION_2_02_0 0x00020200
#define PRIV_VERSION_1_09_1 0x00010901
#define PRIV_VERSION_1_10_0 0x00011000
#define PRIV_VERSION_1_11_0 0x00011100
@ -111,7 +110,6 @@ struct CPURISCVState {
target_ulong badaddr;
target_ulong guest_phys_fault_addr;
target_ulong user_ver;
target_ulong priv_ver;
target_ulong misa;
target_ulong misa_mask;