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target-i386: introduce cpu_get_mem_attrs
Backports commit f794aa4a2fd772a3ec413c4e478cc23857cfee98 from qemu
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@ -29,7 +29,9 @@ typedef struct MemTxAttrs {
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* "didn't specify" if necessary.
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* "didn't specify" if necessary.
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*/
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*/
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unsigned int unspecified:1;
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unsigned int unspecified:1;
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/* ARM/AMBA TrustZone Secure access */
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/* ARM/AMBA TrustZone Secure access
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* x86: System Management Mode access
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*/
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unsigned int secure:1;
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unsigned int secure:1;
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/* Memory access is usermode (unprivileged) */
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/* Memory access is usermode (unprivileged) */
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unsigned int user:1;
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unsigned int user:1;
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@ -1284,6 +1284,13 @@ static inline void cpu_load_efer(CPUX86State *env, uint64_t val)
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}
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}
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}
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}
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static inline MemTxAttrs cpu_get_mem_attrs(CPUX86State *env)
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{
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MemTxAttrs attrs = {0};
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attrs.secure = (env->hflags & HF_SMM_MASK) != 0;
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return attrs;
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}
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/* fpu_helper.c */
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/* fpu_helper.c */
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void cpu_set_mxcsr(CPUX86State *env, uint32_t val);
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void cpu_set_mxcsr(CPUX86State *env, uint32_t val);
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void cpu_set_fpuc(CPUX86State *env, uint16_t val);
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void cpu_set_fpuc(CPUX86State *env, uint16_t val);
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@ -783,7 +783,8 @@ do_check_protect_pse36:
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paddr = vaddr;
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paddr = vaddr;
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//printf(">>> map address %"PRIx64" to %"PRIx64"\n", vaddr, paddr);
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//printf(">>> map address %"PRIx64" to %"PRIx64"\n", vaddr, paddr);
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tlb_set_page(cs, vaddr, paddr, prot, mmu_idx, page_size);
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tlb_set_page_with_attrs(cs, vaddr, paddr, cpu_get_mem_attrs(env),
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prot, mmu_idx, page_size);
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return 0;
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return 0;
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do_fault_rsvd:
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do_fault_rsvd:
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error_code |= PG_ERROR_RSVD_MASK;
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error_code |= PG_ERROR_RSVD_MASK;
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