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arm/translate-a64: add all FP16 ops in simd_scalar_pairwise

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I only needed to do a little light re-factoring to support the
half-precision helpers.

Backports commit 5c36d89567cfd049a7c59ff219639f788225068f from qemu
This commit is contained in:
Alex Bennée 2018-03-08 22:51:05 -05:00 committed by Lioncash
parent 8bbabd7eb3
commit dd29452046
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 53 additions and 29 deletions
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82
qemu/target/arm/translate-a64.c
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@ -6534,24 +6534,26 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
case 0xf: /* FMAXP */
case 0x2c: /* FMINNMP */
case 0x2f: /* FMINP */
/* FP op, size[0] is 32 or 64 bit */
/* FP op, size[0] is 32 or 64 bit*/
if (!u) {
unallocated_encoding(s);
return;
}
if (!fp_access_check(s)) {
return;
if (!arm_dc_feature(s, ARM_FEATURE_V8_FP16)) {
unallocated_encoding(s);
return;
} else {
size = MO_16;
}
} else {
size = extract32(size, 0, 1) ? MO_64 : MO_32;
}
size = extract32(size, 0, 1) ? 3 : 2;
fpst = get_fpstatus_ptr(tcg_ctx, false);
fpst = get_fpstatus_ptr(tcg_ctx, size == MO_16);
break;
default:
unallocated_encoding(s);
return;
}
if (size == 3) {
if (size == MO_64) {
TCGv_i64 tcg_op1 = tcg_temp_new_i64(tcg_ctx);
TCGv_i64 tcg_op2 = tcg_temp_new_i64(tcg_ctx);
TCGv_i64 tcg_res = tcg_temp_new_i64(tcg_ctx);
@ -6592,27 +6594,49 @@ static void disas_simd_scalar_pairwise(DisasContext *s, uint32_t insn)
TCGv_i32 tcg_op2 = tcg_temp_new_i32(tcg_ctx);
TCGv_i32 tcg_res = tcg_temp_new_i32(tcg_ctx);
read_vec_element_i32(s, tcg_op1, rn, 0, MO_32);
read_vec_element_i32(s, tcg_op2, rn, 1, MO_32);
read_vec_element_i32(s, tcg_op1, rn, 0, size);
read_vec_element_i32(s, tcg_op2, rn, 1, size);
switch (opcode) {
case 0xc: /* FMAXNMP */
gen_helper_vfp_maxnums(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0xd: /* FADDP */
gen_helper_vfp_adds(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0xf: /* FMAXP */
gen_helper_vfp_maxs(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x2c: /* FMINNMP */
gen_helper_vfp_minnums(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x2f: /* FMINP */
gen_helper_vfp_mins(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
default:
g_assert_not_reached();
if (size == MO_16) {
switch (opcode) {
case 0xc: /* FMAXNMP */
gen_helper_advsimd_maxnumh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0xd: /* FADDP */
gen_helper_advsimd_addh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0xf: /* FMAXP */
gen_helper_advsimd_maxh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x2c: /* FMINNMP */
gen_helper_advsimd_minnumh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x2f: /* FMINP */
gen_helper_advsimd_minh(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
default:
g_assert_not_reached();
}
} else {
switch (opcode) {
case 0xc: /* FMAXNMP */
gen_helper_vfp_maxnums(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0xd: /* FADDP */
gen_helper_vfp_adds(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0xf: /* FMAXP */
gen_helper_vfp_maxs(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x2c: /* FMINNMP */
gen_helper_vfp_minnums(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
case 0x2f: /* FMINP */
gen_helper_vfp_mins(tcg_ctx, tcg_res, tcg_op1, tcg_op2, fpst);
break;
default:
g_assert_not_reached();
}
}
write_fp_sreg(s, rd, tcg_res);