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target/riscv: Support the v0.6 Hypervisor extension CRSs
Backports 83028098f45a08da209799aeea4801c362d0afeb
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@ -244,9 +244,12 @@
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#define CSR_HIDELEG 0x603
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#define CSR_HIE 0x604
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#define CSR_HCOUNTEREN 0x606
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#define CSR_HGEIE 0x607
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#define CSR_HTVAL 0x643
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#define CSR_HVIP 0x645
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#define CSR_HIP 0x644
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#define CSR_HTINST 0x64A
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#define CSR_HGEIP 0xE12
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#define CSR_HGATP 0x680
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#define CSR_HTIMEDELTA 0x605
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#define CSR_HTIMEDELTAH 0x615
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@ -334,22 +334,13 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
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* was called. Background registers will be used if the guest has
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* forced a two stage translation to be on (in HS or M mode).
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*/
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if (riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH) {
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use_background = true;
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}
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if (mode == PRV_M && access_type != MMU_INST_FETCH) {
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if (get_field(env->mstatus, MSTATUS_MPRV)) {
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mode = get_field(env->mstatus, MSTATUS_MPP);
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if (riscv_has_ext(env, RVH) &&
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MSTATUS_MPV_ISSET(env)) {
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use_background = true;
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}
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}
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}
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if (mode == PRV_S && access_type != MMU_INST_FETCH &&
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riscv_has_ext(env, RVH) && !riscv_cpu_virt_enabled(env)) {
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if (get_field(env->hstatus, HSTATUS_SPRV)) {
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mode = get_field(env->mstatus, SSTATUS_SPP);
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use_background = true;
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}
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}
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@ -602,7 +593,8 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
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}
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break;
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case MMU_DATA_LOAD:
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if (riscv_cpu_virt_enabled(env) && !first_stage) {
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if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env)) &&
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!first_stage) {
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cs->exception_index = RISCV_EXCP_LOAD_GUEST_ACCESS_FAULT;
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} else {
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cs->exception_index = page_fault_exceptions ?
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@ -610,7 +602,8 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong address,
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}
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break;
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case MMU_DATA_STORE:
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if (riscv_cpu_virt_enabled(env) && !first_stage) {
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if ((riscv_cpu_virt_enabled(env) || riscv_cpu_two_stage_lookup(env)) &&
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!first_stage) {
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cs->exception_index = RISCV_EXCP_STORE_GUEST_AMO_ACCESS_FAULT;
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} else {
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cs->exception_index = page_fault_exceptions ?
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@ -697,8 +690,6 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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hwaddr pa = 0;
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int prot, prot2;
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bool pmp_violation = false;
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bool m_mode_two_stage = false;
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bool hs_mode_two_stage = false;
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bool first_stage_error = true;
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int ret = TRANSLATE_FAIL;
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int mode = mmu_idx;
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@ -709,30 +700,21 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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qemu_log_mask(CPU_LOG_MMU, "%s ad %" VADDR_PRIx " rw %d mmu_idx %d\n",
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__func__, address, access_type, mmu_idx);
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/*
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* Determine if we are in M mode and MPRV is set or in HS mode and SPRV is
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* set and we want to access a virtulisation address.
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*/
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if (riscv_has_ext(env, RVH)) {
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m_mode_two_stage = env->priv == PRV_M &&
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access_type != MMU_INST_FETCH &&
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get_field(env->mstatus, MSTATUS_MPRV) &&
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MSTATUS_MPV_ISSET(env);
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hs_mode_two_stage = env->priv == PRV_S &&
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!riscv_cpu_virt_enabled(env) &&
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access_type != MMU_INST_FETCH &&
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get_field(env->hstatus, HSTATUS_SPRV) &&
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get_field(env->hstatus, HSTATUS_SPV);
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}
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if (mode == PRV_M && access_type != MMU_INST_FETCH) {
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if (get_field(env->mstatus, MSTATUS_MPRV)) {
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mode = get_field(env->mstatus, MSTATUS_MPP);
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}
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}
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if (riscv_cpu_virt_enabled(env) || m_mode_two_stage || hs_mode_two_stage) {
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if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
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access_type != MMU_INST_FETCH &&
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get_field(env->mstatus, MSTATUS_MPRV) &&
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MSTATUS_MPV_ISSET(env)) {
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riscv_cpu_set_two_stage_lookup(env, true);
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}
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if (riscv_cpu_virt_enabled(env) ||
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(riscv_cpu_two_stage_lookup(env) && access_type != MMU_INST_FETCH)) {
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/* Two stage lookup */
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ret = get_physical_address(env, &pa, &prot, address, access_type,
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mmu_idx, true, true);
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@ -784,6 +766,14 @@ bool riscv_cpu_tlb_fill(CPUState *cs, vaddr address, int size,
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__func__, address, ret, pa, prot);
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}
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/* We did the two stage lookup based on MPRV, unset the lookup */
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if (riscv_has_ext(env, RVH) && env->priv == PRV_M &&
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access_type != MMU_INST_FETCH &&
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get_field(env->mstatus, MSTATUS_MPRV) &&
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MSTATUS_MPV_ISSET(env)) {
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riscv_cpu_set_two_stage_lookup(env, false);
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}
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if (riscv_feature(env, RISCV_FEATURE_PMP) &&
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(ret == TRANSLATE_SUCCESS) &&
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!pmp_hart_has_privs(env, pa, size, 1 << access_type, mode)) {
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@ -886,12 +886,25 @@ static int write_hideleg(CPURISCVState *env, int csrno, target_ulong val)
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return 0;
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}
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static int rmw_hvip(CPURISCVState *env, int csrno, target_ulong *ret_value,
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target_ulong new_value, target_ulong write_mask)
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{
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int ret = rmw_mip(env, 0, ret_value, new_value,
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write_mask & hip_writable_mask);
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*ret_value &= hip_writable_mask;
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return ret;
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}
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static int rmw_hip(CPURISCVState *env, int csrno, target_ulong *ret_value,
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target_ulong new_value, target_ulong write_mask)
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{
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int ret = rmw_mip(env, 0, ret_value, new_value,
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write_mask & hip_writable_mask);
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*ret_value &= hip_writable_mask;
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return ret;
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}
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@ -919,6 +932,18 @@ static int write_hcounteren(CPURISCVState *env, int csrno, target_ulong val)
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return 0;
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}
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static int read_hgeie(CPURISCVState *env, int csrno, target_ulong *val)
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{
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qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
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return 0;
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}
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static int write_hgeie(CPURISCVState *env, int csrno, target_ulong val)
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{
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qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
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return 0;
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}
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static int read_htval(CPURISCVState *env, int csrno, target_ulong *val)
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{
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*val = env->htval;
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@ -942,6 +967,18 @@ static int write_htinst(CPURISCVState *env, int csrno, target_ulong val)
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return 0;
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}
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static int read_hgeip(CPURISCVState *env, int csrno, target_ulong *val)
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{
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qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
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return 0;
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}
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static int write_hgeip(CPURISCVState *env, int csrno, target_ulong val)
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{
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qemu_log_mask(LOG_UNIMP, "No support for a non-zero GEILEN.");
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return 0;
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}
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static int read_hgatp(CPURISCVState *env, int csrno, target_ulong *val)
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{
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*val = env->hgatp;
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@ -1344,11 +1381,14 @@ static riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
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[CSR_HSTATUS] = { hmode, read_hstatus, write_hstatus },
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[CSR_HEDELEG] = { hmode, read_hedeleg, write_hedeleg },
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[CSR_HIDELEG] = { hmode, read_hideleg, write_hideleg },
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[CSR_HVIP] = { hmode, NULL, NULL, rmw_hvip },
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[CSR_HIP] = { hmode, NULL, NULL, rmw_hip },
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[CSR_HIE] = { hmode, read_hie, write_hie },
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[CSR_HCOUNTEREN] = { hmode, read_hcounteren, write_hcounteren },
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[CSR_HGEIE] = { hmode, read_hgeie, write_hgeie },
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[CSR_HTVAL] = { hmode, read_htval, write_htval },
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[CSR_HTINST] = { hmode, read_htinst, write_htinst },
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[CSR_HGEIP] = { hmode, read_hgeip, write_hgeip },
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[CSR_HGATP] = { hmode, read_hgatp, write_hgatp },
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[CSR_HTIMEDELTA] = { hmode, read_htimedelta, write_htimedelta },
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#if defined(TARGET_RISCV32)
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