yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-01-11 09:45:29 +00:00
Code Issues Packages Projects Releases Wiki Activity

arm: Thumb shift operations should not permit interworking branches

Browse source 
In Thumb mode, the only instructions which can cause an interworking
branch by writing the PC are BLX, BX, BXJ, LDR, POP and LDM. Unlike
ARM mode, data processing instructions which target the PC do not
cause interworking branches.

When we added support for doing interworking branches on writes to
PC from data processing instructions in commit 21aeb3430ce7ba, we
accidentally changed a Thumb instruction to have interworking
branch behaviour for writes to PC. (MOV, MOVS register-shifted
register, encoding T2; this is the standard encoding for
LSL/LSR/ASR/ROR (register).)

For this encoding, behaviour with Rd == R15 is specified as
UNPREDICTABLE, so allowing an interworking branch is within
spec, but it's confusing and differs from our handling of this
class of UNPREDICTABLE for other Thumb ALU operations. Make
it perform a simple (non-interworking) branch like the others.

Backports commit bedb8a6b09c1754c3b9f155750c62dc087706698 from qemu
This commit is contained in:
Peter Maydell 2018-03-02 14:42:38 -05:00 committed by Lioncash
parent 9f938da9e1
commit ddfe550411
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 1 additions and 1 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

2
qemu/target/arm/translate.c
View file

@ -10117,7 +10117,7 @@ static int disas_thumb2_insn(CPUARMState *env, DisasContext *s, uint16_t insn_hw
gen_arm_shift_reg(s, tmp, op, tmp2, logic_cc);
if (logic_cc)
gen_logic_CC(s, tmp);
store_reg_bx(s, rd, tmp);
store_reg(s, rd, tmp);
break;
case 1: /* Sign/zero extend. */
op = (insn >> 20) & 7;