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cpu: move do_unaligned_access to tcg_ops

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make it consistently SOFTMMU-only.

Backports 8535dd702dd054a37a85e0c7971cfb43cc7b50e3
This commit is contained in:
Claudio Fontana 2021-03-04 17:20:01 -05:00 committed by Lioncash
parent ec08ac4995
commit ddfed5f3a6
5 changed files with 11 additions and 10 deletions
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13
qemu/include/qom/cpu.h
View file

@ -129,6 +129,12 @@ typedef struct TcgCpuOperations {
unsigned size, MMUAccessType access_type, unsigned size, MMUAccessType access_type,
int mmu_idx, MemTxAttrs attrs, int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr); MemTxResult response, uintptr_t retaddr);
/**
* @do_unaligned_access: Callback for unaligned access handling
*/
void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
} TcgCpuOperations; } TcgCpuOperations;
@ -142,8 +148,6 @@ typedef struct TcgCpuOperations {
* @has_work: Callback for checking if there is work to do. * @has_work: Callback for checking if there is work to do.
* @do_unassigned_access: Callback for unassigned access handling. * @do_unassigned_access: Callback for unassigned access handling.
* (this is deprecated: new targets should use do_transaction_failed instead) * (this is deprecated: new targets should use do_transaction_failed instead)
* @do_unaligned_access: Callback for unaligned access handling, if
* the target defines #TARGET_ALIGNED_ONLY.
* @memory_rw_debug: Callback for GDB memory access. * @memory_rw_debug: Callback for GDB memory access.
* @dump_state: Callback for dumping state. * @dump_state: Callback for dumping state.
* @dump_statistics: Callback for dumping statistics. * @dump_statistics: Callback for dumping statistics.
@ -185,9 +189,6 @@ typedef struct CPUClass {
int reset_dump_flags; int reset_dump_flags;
bool (*has_work)(CPUState *cpu); bool (*has_work)(CPUState *cpu);
CPUUnassignedAccess do_unassigned_access; CPUUnassignedAccess do_unassigned_access;
void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
MMUAccessType access_type,
int mmu_idx, uintptr_t retaddr);
int (*memory_rw_debug)(CPUState *cpu, vaddr addr, int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
uint8_t *buf, int len, bool is_write); uint8_t *buf, int len, bool is_write);
void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
@ -754,7 +755,7 @@ static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
{ {
CPUClass *cc = CPU_GET_CLASS(cpu->uc, cpu); CPUClass *cc = CPU_GET_CLASS(cpu->uc, cpu);
cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr); cc->tcg_ops.do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
} }
static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr, static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,

2
qemu/target/arm/cpu.c
View file

@ -2113,9 +2113,9 @@ static void arm_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data
cc->tcg_ops.tlb_fill = arm_cpu_tlb_fill; cc->tcg_ops.tlb_fill = arm_cpu_tlb_fill;
cc->tcg_ops.debug_excp_handler = arm_debug_excp_handler; cc->tcg_ops.debug_excp_handler = arm_debug_excp_handler;
cc->debug_check_watchpoint = arm_debug_check_watchpoint; cc->debug_check_watchpoint = arm_debug_check_watchpoint;
cc->do_unaligned_access = arm_cpu_do_unaligned_access;
#if !defined(CONFIG_USER_ONLY) #if !defined(CONFIG_USER_ONLY)
cc->tcg_ops.do_transaction_failed = arm_cpu_do_transaction_failed; cc->tcg_ops.do_transaction_failed = arm_cpu_do_transaction_failed;
cc->tcg_ops.do_unaligned_access = arm_cpu_do_unaligned_access;
cc->adjust_watchpoint_address = arm_adjust_watchpoint_address; cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt; cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
#endif #endif

2
qemu/target/mips/cpu.c
View file

@ -175,7 +175,6 @@ static void mips_cpu_class_init(struct uc_struct *uc, ObjectClass *c, void *data
cc->has_work = mips_cpu_has_work; cc->has_work = mips_cpu_has_work;
cc->set_pc = mips_cpu_set_pc; cc->set_pc = mips_cpu_set_pc;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
cc->do_unaligned_access = mips_cpu_do_unaligned_access;
cc->get_phys_page_debug = mips_cpu_get_phys_page_debug; cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
#endif #endif
#ifdef CONFIG_TCG #ifdef CONFIG_TCG
@ -186,6 +185,7 @@ static void mips_cpu_class_init(struct uc_struct *uc, ObjectClass *c, void *data
cc->tcg_ops.tlb_fill = mips_cpu_tlb_fill; cc->tcg_ops.tlb_fill = mips_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
cc->tcg_ops.do_transaction_failed = mips_cpu_do_transaction_failed; cc->tcg_ops.do_transaction_failed = mips_cpu_do_transaction_failed;
cc->tcg_ops.do_unaligned_access = mips_cpu_do_unaligned_access;
#endif /* CONFIG_USER_ONLY */ #endif /* CONFIG_USER_ONLY */
#endif /* CONFIG_TCG */ #endif /* CONFIG_TCG */
} }

2
qemu/target/riscv/cpu.c
View file

@ -369,7 +369,7 @@ static void riscv_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *da
//cc->disas_set_info = riscv_cpu_disas_set_info; //cc->disas_set_info = riscv_cpu_disas_set_info;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
cc->do_unassigned_access = riscv_cpu_unassigned_access; cc->do_unassigned_access = riscv_cpu_unassigned_access;
cc->do_unaligned_access = riscv_cpu_do_unaligned_access; cc->tcg_ops.do_unaligned_access = riscv_cpu_do_unaligned_access;
cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug; cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
#endif #endif
cc->tcg_ops.initialize = riscv_translate_init; cc->tcg_ops.initialize = riscv_translate_init;

2
qemu/target/sparc/cpu.c
View file

@ -851,7 +851,7 @@ static void sparc_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *da
cc->tcg_ops.tlb_fill = sparc_cpu_tlb_fill; cc->tcg_ops.tlb_fill = sparc_cpu_tlb_fill;
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
cc->tcg_ops.do_transaction_failed = sparc_cpu_do_transaction_failed; cc->tcg_ops.do_transaction_failed = sparc_cpu_do_transaction_failed;
cc->do_unaligned_access = sparc_cpu_do_unaligned_access; cc->tcg_ops.do_unaligned_access = sparc_cpu_do_unaligned_access;
cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug; cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
// Unicorn: commented out // Unicorn: commented out
//cc->vmsd = &vmstate_sparc_cpu; //cc->vmsd = &vmstate_sparc_cpu;