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cpu: move do_unaligned_access to tcg_ops
make it consistently SOFTMMU-only. Backports 8535dd702dd054a37a85e0c7971cfb43cc7b50e3
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ddfed5f3a6
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@ -129,6 +129,12 @@ typedef struct TcgCpuOperations {
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unsigned size, MMUAccessType access_type,
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int mmu_idx, MemTxAttrs attrs,
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MemTxResult response, uintptr_t retaddr);
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/**
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* @do_unaligned_access: Callback for unaligned access handling
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*/
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void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
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MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr);
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} TcgCpuOperations;
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@ -142,8 +148,6 @@ typedef struct TcgCpuOperations {
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* @has_work: Callback for checking if there is work to do.
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* @do_unassigned_access: Callback for unassigned access handling.
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* (this is deprecated: new targets should use do_transaction_failed instead)
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* @do_unaligned_access: Callback for unaligned access handling, if
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* the target defines #TARGET_ALIGNED_ONLY.
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* @memory_rw_debug: Callback for GDB memory access.
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* @dump_state: Callback for dumping state.
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* @dump_statistics: Callback for dumping statistics.
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@ -185,9 +189,6 @@ typedef struct CPUClass {
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int reset_dump_flags;
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bool (*has_work)(CPUState *cpu);
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CPUUnassignedAccess do_unassigned_access;
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void (*do_unaligned_access)(CPUState *cpu, vaddr addr,
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MMUAccessType access_type,
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int mmu_idx, uintptr_t retaddr);
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int (*memory_rw_debug)(CPUState *cpu, vaddr addr,
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uint8_t *buf, int len, bool is_write);
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void (*dump_state)(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf,
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@ -754,7 +755,7 @@ static inline void cpu_unaligned_access(CPUState *cpu, vaddr addr,
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{
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CPUClass *cc = CPU_GET_CLASS(cpu->uc, cpu);
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cc->do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
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cc->tcg_ops.do_unaligned_access(cpu, addr, access_type, mmu_idx, retaddr);
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}
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static inline void cpu_transaction_failed(CPUState *cpu, hwaddr physaddr,
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@ -2113,9 +2113,9 @@ static void arm_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *data
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cc->tcg_ops.tlb_fill = arm_cpu_tlb_fill;
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cc->tcg_ops.debug_excp_handler = arm_debug_excp_handler;
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cc->debug_check_watchpoint = arm_debug_check_watchpoint;
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cc->do_unaligned_access = arm_cpu_do_unaligned_access;
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#if !defined(CONFIG_USER_ONLY)
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cc->tcg_ops.do_transaction_failed = arm_cpu_do_transaction_failed;
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cc->tcg_ops.do_unaligned_access = arm_cpu_do_unaligned_access;
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cc->adjust_watchpoint_address = arm_adjust_watchpoint_address;
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cc->tcg_ops.do_interrupt = arm_cpu_do_interrupt;
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#endif
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@ -175,7 +175,6 @@ static void mips_cpu_class_init(struct uc_struct *uc, ObjectClass *c, void *data
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cc->has_work = mips_cpu_has_work;
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cc->set_pc = mips_cpu_set_pc;
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#ifndef CONFIG_USER_ONLY
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cc->do_unaligned_access = mips_cpu_do_unaligned_access;
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cc->get_phys_page_debug = mips_cpu_get_phys_page_debug;
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#endif
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#ifdef CONFIG_TCG
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@ -186,6 +185,7 @@ static void mips_cpu_class_init(struct uc_struct *uc, ObjectClass *c, void *data
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cc->tcg_ops.tlb_fill = mips_cpu_tlb_fill;
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#ifndef CONFIG_USER_ONLY
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cc->tcg_ops.do_transaction_failed = mips_cpu_do_transaction_failed;
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cc->tcg_ops.do_unaligned_access = mips_cpu_do_unaligned_access;
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#endif /* CONFIG_USER_ONLY */
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#endif /* CONFIG_TCG */
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}
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@ -369,7 +369,7 @@ static void riscv_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *da
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//cc->disas_set_info = riscv_cpu_disas_set_info;
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#ifndef CONFIG_USER_ONLY
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cc->do_unassigned_access = riscv_cpu_unassigned_access;
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cc->do_unaligned_access = riscv_cpu_do_unaligned_access;
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cc->tcg_ops.do_unaligned_access = riscv_cpu_do_unaligned_access;
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cc->get_phys_page_debug = riscv_cpu_get_phys_page_debug;
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#endif
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cc->tcg_ops.initialize = riscv_translate_init;
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@ -851,7 +851,7 @@ static void sparc_cpu_class_init(struct uc_struct *uc, ObjectClass *oc, void *da
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cc->tcg_ops.tlb_fill = sparc_cpu_tlb_fill;
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#ifndef CONFIG_USER_ONLY
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cc->tcg_ops.do_transaction_failed = sparc_cpu_do_transaction_failed;
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cc->do_unaligned_access = sparc_cpu_do_unaligned_access;
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cc->tcg_ops.do_unaligned_access = sparc_cpu_do_unaligned_access;
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cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug;
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// Unicorn: commented out
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//cc->vmsd = &vmstate_sparc_cpu;
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