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target/riscv: Convert RVXI fence insns to decodetree

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Backports commit 0c865e856a7e97d37c4dea4cf2ff875faa6e72ed from qemu
This commit is contained in:
Bastian Koppelmann 2019-03-18 16:06:49 -04:00 committed by Lioncash
parent 11e2b9c410
commit de580ee378
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GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 27 additions and 15 deletions
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2
qemu/target/riscv/insn32.decode
View file

@ -82,3 +82,5 @@ srl 0000000 ..... ..... 101 ..... 0110011 @r
sra 0100000 ..... ..... 101 ..... 0110011 @r
or 0000000 ..... ..... 110 ..... 0110011 @r
and 0000000 ..... ..... 111 ..... 0110011 @r
fence ---- pred:4 succ:4 ----- 000 ----- 0001111
fence_i ---- ---- ---- ----- 001 ----- 0001111

27
qemu/target/riscv/insn_trans/trans_rvi.inc.c
View file

@ -22,7 +22,7 @@ static bool trans_lui(DisasContext *ctx, arg_lui *a)
{
if (a->rd != 0) {
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr[a->rd], a->imm);
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr_risc[a->rd], a->imm);
}
return true;
}
@ -31,7 +31,7 @@ static bool trans_auipc(DisasContext *ctx, arg_auipc *a)
{
if (a->rd != 0) {
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr[a->rd], a->imm + ctx->base.pc_next);
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_gpr_risc[a->rd], a->imm + ctx->base.pc_next);
}
return true;
}
@ -320,3 +320,26 @@ static bool trans_sraw(DisasContext *ctx, arg_sraw *a)
return true;
}
#endif
static bool trans_fence(DisasContext *ctx, arg_fence *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
/* FENCE is a full memory barrier. */
tcg_gen_mb(tcg_ctx, TCG_MO_ALL | TCG_BAR_SC);
return true;
}
static bool trans_fence_i(DisasContext *ctx, arg_fence_i *a)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
/*
* FENCE_I is a no-op in QEMU,
* however we need to end the translation block
*/
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_pc_risc, ctx->pc_succ_insn);
tcg_gen_exit_tb(tcg_ctx, NULL, 0);
ctx->base.is_jmp = DISAS_NORETURN;
return true;
}

13
qemu/target/riscv/translate.c
View file

@ -1962,7 +1962,6 @@ bool decode_insn32(DisasContext *ctx, uint32_t insn);
static void decode_RV32_64G(DisasContext *ctx)
{
TCGContext *tcg_ctx = ctx->uc->tcg_ctx;
int rs1;
int rs2;
int rd;
@ -2023,18 +2022,6 @@ static void decode_RV32_64G(DisasContext *ctx)
gen_fp_arith(ctx, MASK_OP_FP_ARITH(ctx->opcode), rd, rs1, rs2,
GET_RM(ctx->opcode));
break;
case OPC_RISC_FENCE:
if (ctx->opcode & 0x1000) {
/* FENCE_I is a no-op in QEMU,
* however we need to end the translation block */
tcg_gen_movi_tl(tcg_ctx, tcg_ctx->cpu_pc_risc, ctx->pc_succ_insn);
tcg_gen_exit_tb(tcg_ctx, NULL, 0);
ctx->base.is_jmp = DISAS_NORETURN;
} else {
/* FENCE is a full memory barrier. */
tcg_gen_mb(tcg_ctx, TCG_MO_ALL | TCG_BAR_SC);
}
break;
case OPC_RISC_SYSTEM:
gen_system(ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1,
(ctx->opcode & 0xFFF00000) >> 20);