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target/arm: Convert T16, Conditional branches, Supervisor call

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Backports commit 629fcaa71ca9a5d6695d1664257b6a5327f38bd6 from qemu
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Richard Henderson 2019-11-20 12:36:46 -05:00 committed by Lioncash
parent 336d6b3625
commit dec55633dc
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GPG key ID: 4E3C3CC1031BA9C7
2 changed files with 15 additions and 23 deletions
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12
qemu/target/arm/t16.decode
View file

@ -28,11 +28,13 @@
&rr !extern rd rm &rr !extern rd rm
&ri !extern rd imm &ri !extern rd imm
&r !extern rm &r !extern rm
&i !extern imm
&ldst_rr !extern p w u rn rt rm shimm shtype &ldst_rr !extern p w u rn rt rm shimm shtype
&ldst_ri !extern p w u rn rt imm &ldst_ri !extern p w u rn rt imm
&ldst_block !extern rn i b u w list &ldst_block !extern rn i b u w list
&setend !extern E &setend !extern E
&cps !extern mode imod M A I F &cps !extern mode imod M A I F
&ci !extern cond imm
# Set S if the instruction is outside of an IT block. # Set S if the instruction is outside of an IT block.
%s !function=t16_setflags %s !function=t16_setflags
@ -231,3 +233,13 @@ STM 1011 010 ......... \
&ldst_block i=0 b=1 u=0 w=1 rn=13 list=%push_list &ldst_block i=0 b=1 u=0 w=1 rn=13 list=%push_list
LDM_t16 1011 110 ......... \ LDM_t16 1011 110 ......... \
&ldst_block i=1 b=0 u=0 w=1 rn=13 list=%pop_list &ldst_block i=1 b=0 u=0 w=1 rn=13 list=%pop_list
# Conditional branches, Supervisor call
%imm8_0x2 0:s8 !function=times_2
{
UDF 1101 1110 ---- ----
SVC 1101 1111 imm:8 &i
B_cond_thumb 1101 cond:4 ........ &ci imm=%imm8_0x2
}

26
qemu/target/arm/translate.c
View file

@ -11074,7 +11074,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
static void disas_thumb_insn(DisasContext *s, uint32_t insn) static void disas_thumb_insn(DisasContext *s, uint32_t insn)
{ {
TCGContext *tcg_ctx = s->uc->tcg_ctx; TCGContext *tcg_ctx = s->uc->tcg_ctx;
uint32_t val, op, rm, rd, shift, cond; uint32_t val, op, rm, rd, shift;
int32_t offset; int32_t offset;
TCGv_i32 tmp; TCGv_i32 tmp;
TCGv_i32 tmp2; TCGv_i32 tmp2;
@ -11214,28 +11214,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
} }
break; break;
case 13: case 13: /* conditional branch or swi, in decodetree */
/* conditional branch or swi */ goto illegal_op;
cond = (insn >> 8) & 0xf;
if (cond == 0xe)
goto undef;
if (cond == 0xf) {
/* swi */
gen_set_pc_im(s, s->base.pc_next);
s->svc_imm = extract32(insn, 0, 8);
s->base.is_jmp = DISAS_SWI;
break;
}
/* generate a conditional jump to next instruction */
arm_skip_unless(s, cond);
/* jump to the offset */
val = read_pc(s);
offset = ((int32_t)insn << 24) >> 24;
val += offset << 1;
gen_jmp(s, val);
break;
case 14: case 14:
if (insn & (1 << 11)) { if (insn & (1 << 11)) {