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target/arm: Convert T16, Conditional branches, Supervisor call
Backports commit 629fcaa71ca9a5d6695d1664257b6a5327f38bd6 from qemu
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@ -28,11 +28,13 @@
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&rr !extern rd rm
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&ri !extern rd imm
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&r !extern rm
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&i !extern imm
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&ldst_rr !extern p w u rn rt rm shimm shtype
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&ldst_ri !extern p w u rn rt imm
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&ldst_block !extern rn i b u w list
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&setend !extern E
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&cps !extern mode imod M A I F
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&ci !extern cond imm
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# Set S if the instruction is outside of an IT block.
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%s !function=t16_setflags
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@ -231,3 +233,13 @@ STM 1011 010 ......... \
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&ldst_block i=0 b=1 u=0 w=1 rn=13 list=%push_list
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LDM_t16 1011 110 ......... \
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&ldst_block i=1 b=0 u=0 w=1 rn=13 list=%pop_list
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# Conditional branches, Supervisor call
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%imm8_0x2 0:s8 !function=times_2
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{
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UDF 1101 1110 ---- ----
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SVC 1101 1111 imm:8 &i
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B_cond_thumb 1101 cond:4 ........ &ci imm=%imm8_0x2
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}
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@ -11074,7 +11074,7 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
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static void disas_thumb_insn(DisasContext *s, uint32_t insn)
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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uint32_t val, op, rm, rd, shift, cond;
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uint32_t val, op, rm, rd, shift;
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int32_t offset;
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TCGv_i32 tmp;
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TCGv_i32 tmp2;
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@ -11214,28 +11214,8 @@ static void disas_thumb_insn(DisasContext *s, uint32_t insn)
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}
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break;
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case 13:
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/* conditional branch or swi */
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cond = (insn >> 8) & 0xf;
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if (cond == 0xe)
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goto undef;
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if (cond == 0xf) {
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/* swi */
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gen_set_pc_im(s, s->base.pc_next);
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s->svc_imm = extract32(insn, 0, 8);
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s->base.is_jmp = DISAS_SWI;
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break;
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}
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/* generate a conditional jump to next instruction */
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arm_skip_unless(s, cond);
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/* jump to the offset */
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val = read_pc(s);
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offset = ((int32_t)insn << 24) >> 24;
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val += offset << 1;
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gen_jmp(s, val);
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break;
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case 13: /* conditional branch or swi, in decodetree */
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goto illegal_op;
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case 14:
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if (insn & (1 << 11)) {
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