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target/arm: Relax r13 restriction for ldrex/strex for v8.0
Armv8-A removes UNPREDICTABLE for R13 for these cases. Backports commit d46ad79efac7aaf9f0eb9f5a96a576e9f39200e0 from qemu
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@ -9206,15 +9206,17 @@ static bool op_strex(DisasContext *s, arg_STREX *a, MemOp mop, bool rel)
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{
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv_i32 addr;
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TCGv_i32 addr;
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/* Some cases stopped being UNPREDICTABLE in v8A (but not v8M) */
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bool v8a = ENABLE_ARCH_8 && !arm_dc_feature(s, ARM_FEATURE_M);
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/* We UNDEF for these UNPREDICTABLE cases. */
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/* We UNDEF for these UNPREDICTABLE cases. */
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if (a->rd == 15 || a->rn == 15 || a->rt == 15
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if (a->rd == 15 || a->rn == 15 || a->rt == 15
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|| a->rd == a->rn || a->rd == a->rt
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|| a->rd == a->rn || a->rd == a->rt
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|| (s->thumb && (a->rd == 13 || a->rt == 13))
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|| (!v8a && s->thumb && (a->rd == 13 || a->rt == 13))
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|| (mop == MO_64
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|| (mop == MO_64
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&& (a->rt2 == 15
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&& (a->rt2 == 15
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|| a->rd == a->rt2
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|| a->rd == a->rt2
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|| (s->thumb && a->rt2 == 13)))) {
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|| (!v8a && s->thumb && a->rt2 == 13)))) {
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unallocated_encoding(s);
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unallocated_encoding(s);
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return true;
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return true;
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}
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}
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@ -9365,13 +9367,15 @@ static bool op_ldrex(DisasContext *s, arg_LDREX *a, MemOp mop, bool acq)
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{
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{
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGContext *tcg_ctx = s->uc->tcg_ctx;
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TCGv_i32 addr;
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TCGv_i32 addr;
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/* Some cases stopped being UNPREDICTABLE in v8A (but not v8M) */
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bool v8a = ENABLE_ARCH_8 && !arm_dc_feature(s, ARM_FEATURE_M);
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/* We UNDEF for these UNPREDICTABLE cases. */
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/* We UNDEF for these UNPREDICTABLE cases. */
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if (a->rn == 15 || a->rt == 15
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if (a->rn == 15 || a->rt == 15
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|| (s->thumb && a->rt == 13)
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|| (!v8a && s->thumb && a->rt == 13)
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|| (mop == MO_64
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|| (mop == MO_64
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&& (a->rt2 == 15 || a->rt == a->rt2
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&& (a->rt2 == 15 || a->rt == a->rt2
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|| (s->thumb && a->rt2 == 13)))) {
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|| (!v8a && s->thumb && a->rt2 == 13)))) {
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unallocated_encoding(s);
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unallocated_encoding(s);
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return true;
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return true;
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}
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}
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