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exec: introduce tlb_init

Paves the way for the addition of a per-TLB lock.

Backports commit 5005e2537d090bee87aca3b924dcd17920fd146a from qemu
This commit is contained in:
Emilio G. Cota 2018-10-23 14:41:10 -04:00 committed by Lioncash
parent e5b43d2794
commit dfb3954571
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
17 changed files with 24 additions and 0 deletions

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@ -3123,6 +3123,7 @@
#define thumb2_logic_op thumb2_logic_op_aarch64
#define ti925t_initfn ti925t_initfn_aarch64
#define tlb_add_large_page tlb_add_large_page_aarch64
#define tlb_init tlb_init_aarch64
#define tlb_fill tlb_fill_aarch64
#define tlb_flush tlb_flush_aarch64
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_aarch64

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@ -3123,6 +3123,7 @@
#define thumb2_logic_op thumb2_logic_op_aarch64eb
#define ti925t_initfn ti925t_initfn_aarch64eb
#define tlb_add_large_page tlb_add_large_page_aarch64eb
#define tlb_init tlb_init_aarch64eb
#define tlb_fill tlb_fill_aarch64eb
#define tlb_flush tlb_flush_aarch64eb
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_aarch64eb

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@ -66,6 +66,10 @@ static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
target_ulong size);
static void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr);
void tlb_init(CPUState *cpu)
{
}
/* This is OK because CPU architectures generally permit an
* implementation to drop entries from the TLB at any time, so
* flushing more entries than required is only an efficiency issue,

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@ -3123,6 +3123,7 @@
#define thumb2_logic_op thumb2_logic_op_arm
#define ti925t_initfn ti925t_initfn_arm
#define tlb_add_large_page tlb_add_large_page_arm
#define tlb_init tlb_init_arm
#define tlb_fill tlb_fill_arm
#define tlb_flush tlb_flush_arm
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_arm

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@ -3123,6 +3123,7 @@
#define thumb2_logic_op thumb2_logic_op_armeb
#define ti925t_initfn ti925t_initfn_armeb
#define tlb_add_large_page tlb_add_large_page_armeb
#define tlb_init tlb_init_armeb
#define tlb_fill tlb_fill_armeb
#define tlb_flush tlb_flush_armeb
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_armeb

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@ -644,6 +644,7 @@ void cpu_exec_init(CPUState *cpu, Error **errp, void *opaque)
cc->tcg_initialized = true;
cc->tcg_initialize(uc);
}
tlb_init(cpu);
#ifndef CONFIG_USER_ONLY

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@ -3129,6 +3129,7 @@ symbols = (
'thumb2_logic_op',
'ti925t_initfn',
'tlb_add_large_page',
'tlb_init',
'tlb_fill',
'tlb_flush',
'tlb_flush_by_mmuidx',

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@ -109,6 +109,11 @@ void cpu_address_space_init(CPUState *cpu, int asidx,
#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
/* cputlb.c */
/**
* tlb_init - initialize a CPU's TLB
* @cpu: CPU whose TLB should be initialized
*/
void tlb_init(CPUState *cpu);
/**
* tlb_flush_page:
* @cpu: CPU whose TLB should be flushed

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@ -3123,6 +3123,7 @@
#define thumb2_logic_op thumb2_logic_op_m68k
#define ti925t_initfn ti925t_initfn_m68k
#define tlb_add_large_page tlb_add_large_page_m68k
#define tlb_init tlb_init_m68k
#define tlb_fill tlb_fill_m68k
#define tlb_flush tlb_flush_m68k
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_m68k

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@ -3123,6 +3123,7 @@
#define thumb2_logic_op thumb2_logic_op_mips
#define ti925t_initfn ti925t_initfn_mips
#define tlb_add_large_page tlb_add_large_page_mips
#define tlb_init tlb_init_mips
#define tlb_fill tlb_fill_mips
#define tlb_flush tlb_flush_mips
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mips

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@ -3123,6 +3123,7 @@
#define thumb2_logic_op thumb2_logic_op_mips64
#define ti925t_initfn ti925t_initfn_mips64
#define tlb_add_large_page tlb_add_large_page_mips64
#define tlb_init tlb_init_mips64
#define tlb_fill tlb_fill_mips64
#define tlb_flush tlb_flush_mips64
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mips64

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@ -3123,6 +3123,7 @@
#define thumb2_logic_op thumb2_logic_op_mips64el
#define ti925t_initfn ti925t_initfn_mips64el
#define tlb_add_large_page tlb_add_large_page_mips64el
#define tlb_init tlb_init_mips64el
#define tlb_fill tlb_fill_mips64el
#define tlb_flush tlb_flush_mips64el
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mips64el

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@ -3123,6 +3123,7 @@
#define thumb2_logic_op thumb2_logic_op_mipsel
#define ti925t_initfn ti925t_initfn_mipsel
#define tlb_add_large_page tlb_add_large_page_mipsel
#define tlb_init tlb_init_mipsel
#define tlb_fill tlb_fill_mipsel
#define tlb_flush tlb_flush_mipsel
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mipsel

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@ -3123,6 +3123,7 @@
#define thumb2_logic_op thumb2_logic_op_powerpc
#define ti925t_initfn ti925t_initfn_powerpc
#define tlb_add_large_page tlb_add_large_page_powerpc
#define tlb_init tlb_init_powerpc
#define tlb_fill tlb_fill_powerpc
#define tlb_flush tlb_flush_powerpc
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_powerpc

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@ -3123,6 +3123,7 @@
#define thumb2_logic_op thumb2_logic_op_sparc
#define ti925t_initfn ti925t_initfn_sparc
#define tlb_add_large_page tlb_add_large_page_sparc
#define tlb_init tlb_init_sparc
#define tlb_fill tlb_fill_sparc
#define tlb_flush tlb_flush_sparc
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_sparc

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@ -3123,6 +3123,7 @@
#define thumb2_logic_op thumb2_logic_op_sparc64
#define ti925t_initfn ti925t_initfn_sparc64
#define tlb_add_large_page tlb_add_large_page_sparc64
#define tlb_init tlb_init_sparc64
#define tlb_fill tlb_fill_sparc64
#define tlb_flush tlb_flush_sparc64
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_sparc64

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@ -3123,6 +3123,7 @@
#define thumb2_logic_op thumb2_logic_op_x86_64
#define ti925t_initfn ti925t_initfn_x86_64
#define tlb_add_large_page tlb_add_large_page_x86_64
#define tlb_init tlb_init_x86_64
#define tlb_fill tlb_fill_x86_64
#define tlb_flush tlb_flush_x86_64
#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_x86_64