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https://github.com/yuzu-emu/unicorn.git
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exec: introduce tlb_init
Paves the way for the addition of a per-TLB lock. Backports commit 5005e2537d090bee87aca3b924dcd17920fd146a from qemu
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e5b43d2794
commit
dfb3954571
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@ -3123,6 +3123,7 @@
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#define thumb2_logic_op thumb2_logic_op_aarch64
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#define ti925t_initfn ti925t_initfn_aarch64
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#define tlb_add_large_page tlb_add_large_page_aarch64
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#define tlb_init tlb_init_aarch64
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#define tlb_fill tlb_fill_aarch64
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#define tlb_flush tlb_flush_aarch64
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_aarch64
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@ -3123,6 +3123,7 @@
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#define thumb2_logic_op thumb2_logic_op_aarch64eb
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#define ti925t_initfn ti925t_initfn_aarch64eb
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#define tlb_add_large_page tlb_add_large_page_aarch64eb
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#define tlb_init tlb_init_aarch64eb
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#define tlb_fill tlb_fill_aarch64eb
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#define tlb_flush tlb_flush_aarch64eb
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_aarch64eb
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@ -66,6 +66,10 @@ static void tlb_add_large_page(CPUArchState *env, target_ulong vaddr,
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target_ulong size);
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static void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr);
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void tlb_init(CPUState *cpu)
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{
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}
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/* This is OK because CPU architectures generally permit an
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* implementation to drop entries from the TLB at any time, so
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* flushing more entries than required is only an efficiency issue,
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@ -3123,6 +3123,7 @@
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#define thumb2_logic_op thumb2_logic_op_arm
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#define ti925t_initfn ti925t_initfn_arm
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#define tlb_add_large_page tlb_add_large_page_arm
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#define tlb_init tlb_init_arm
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#define tlb_fill tlb_fill_arm
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#define tlb_flush tlb_flush_arm
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_arm
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@ -3123,6 +3123,7 @@
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#define thumb2_logic_op thumb2_logic_op_armeb
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#define ti925t_initfn ti925t_initfn_armeb
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#define tlb_add_large_page tlb_add_large_page_armeb
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#define tlb_init tlb_init_armeb
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#define tlb_fill tlb_fill_armeb
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#define tlb_flush tlb_flush_armeb
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_armeb
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@ -644,6 +644,7 @@ void cpu_exec_init(CPUState *cpu, Error **errp, void *opaque)
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cc->tcg_initialized = true;
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cc->tcg_initialize(uc);
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}
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tlb_init(cpu);
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#ifndef CONFIG_USER_ONLY
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@ -3129,6 +3129,7 @@ symbols = (
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'thumb2_logic_op',
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'ti925t_initfn',
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'tlb_add_large_page',
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'tlb_init',
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'tlb_fill',
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'tlb_flush',
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'tlb_flush_by_mmuidx',
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@ -109,6 +109,11 @@ void cpu_address_space_init(CPUState *cpu, int asidx,
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#if !defined(CONFIG_USER_ONLY) && defined(CONFIG_TCG)
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/* cputlb.c */
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/**
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* tlb_init - initialize a CPU's TLB
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* @cpu: CPU whose TLB should be initialized
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*/
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void tlb_init(CPUState *cpu);
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/**
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* tlb_flush_page:
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* @cpu: CPU whose TLB should be flushed
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@ -3123,6 +3123,7 @@
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#define thumb2_logic_op thumb2_logic_op_m68k
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#define ti925t_initfn ti925t_initfn_m68k
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#define tlb_add_large_page tlb_add_large_page_m68k
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#define tlb_init tlb_init_m68k
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#define tlb_fill tlb_fill_m68k
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#define tlb_flush tlb_flush_m68k
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_m68k
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@ -3123,6 +3123,7 @@
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#define thumb2_logic_op thumb2_logic_op_mips
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#define ti925t_initfn ti925t_initfn_mips
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#define tlb_add_large_page tlb_add_large_page_mips
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#define tlb_init tlb_init_mips
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#define tlb_fill tlb_fill_mips
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#define tlb_flush tlb_flush_mips
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mips
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@ -3123,6 +3123,7 @@
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#define thumb2_logic_op thumb2_logic_op_mips64
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#define ti925t_initfn ti925t_initfn_mips64
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#define tlb_add_large_page tlb_add_large_page_mips64
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#define tlb_init tlb_init_mips64
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#define tlb_fill tlb_fill_mips64
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#define tlb_flush tlb_flush_mips64
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mips64
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@ -3123,6 +3123,7 @@
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#define thumb2_logic_op thumb2_logic_op_mips64el
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#define ti925t_initfn ti925t_initfn_mips64el
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#define tlb_add_large_page tlb_add_large_page_mips64el
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#define tlb_init tlb_init_mips64el
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#define tlb_fill tlb_fill_mips64el
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#define tlb_flush tlb_flush_mips64el
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mips64el
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@ -3123,6 +3123,7 @@
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#define thumb2_logic_op thumb2_logic_op_mipsel
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#define ti925t_initfn ti925t_initfn_mipsel
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#define tlb_add_large_page tlb_add_large_page_mipsel
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#define tlb_init tlb_init_mipsel
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#define tlb_fill tlb_fill_mipsel
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#define tlb_flush tlb_flush_mipsel
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_mipsel
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@ -3123,6 +3123,7 @@
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#define thumb2_logic_op thumb2_logic_op_powerpc
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#define ti925t_initfn ti925t_initfn_powerpc
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#define tlb_add_large_page tlb_add_large_page_powerpc
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#define tlb_init tlb_init_powerpc
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#define tlb_fill tlb_fill_powerpc
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#define tlb_flush tlb_flush_powerpc
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_powerpc
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@ -3123,6 +3123,7 @@
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#define thumb2_logic_op thumb2_logic_op_sparc
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#define ti925t_initfn ti925t_initfn_sparc
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#define tlb_add_large_page tlb_add_large_page_sparc
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#define tlb_init tlb_init_sparc
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#define tlb_fill tlb_fill_sparc
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#define tlb_flush tlb_flush_sparc
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_sparc
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#define thumb2_logic_op thumb2_logic_op_sparc64
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#define ti925t_initfn ti925t_initfn_sparc64
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#define tlb_add_large_page tlb_add_large_page_sparc64
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#define tlb_init tlb_init_sparc64
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#define tlb_fill tlb_fill_sparc64
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#define tlb_flush tlb_flush_sparc64
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_sparc64
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@ -3123,6 +3123,7 @@
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#define thumb2_logic_op thumb2_logic_op_x86_64
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#define ti925t_initfn ti925t_initfn_x86_64
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#define tlb_add_large_page tlb_add_large_page_x86_64
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#define tlb_init tlb_init_x86_64
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#define tlb_fill tlb_fill_x86_64
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#define tlb_flush tlb_flush_x86_64
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#define tlb_flush_by_mmuidx tlb_flush_by_mmuidx_x86_64
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