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target-arm: Add the Cortex-R5F
Add the Cortex-R5F with the optional FPU enabled. Backports commit ebac5458c7517ed7b8ee06eb90beacc7472b295d from qemu
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@ -1109,6 +1109,14 @@ static void cortex_r5_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
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define_arm_cp_regs(cpu, cortexr5_cp_reginfo);
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}
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}
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static void cortex_r5f_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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{
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ARMCPU *cpu = ARM_CPU(uc, obj);
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cortex_r5_initfn(uc, obj, opaque);
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set_feature(&cpu->env, ARM_FEATURE_VFP3);
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}
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static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
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static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
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{ "L2LOCKDOWN", 15,9,0, 0,1,0, 0,
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{ "L2LOCKDOWN", 15,9,0, 0,1,0, 0,
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ARM_CP_CONST, PL1_RW, 0, NULL, 0, },
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ARM_CP_CONST, PL1_RW, 0, NULL, 0, },
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@ -1562,6 +1570,7 @@ static const ARMCPUInfo arm_cpus[] = {
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{ "cortex-m4", cortex_m4_initfn, arm_v7m_class_init },
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{ "cortex-m4", cortex_m4_initfn, arm_v7m_class_init },
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{ "cortex-m33", cortex_m33_initfn, arm_v7m_class_init },
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{ "cortex-m33", cortex_m33_initfn, arm_v7m_class_init },
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{ "cortex-r5", cortex_r5_initfn },
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{ "cortex-r5", cortex_r5_initfn },
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{ "cortex-r5f", cortex_r5f_initfn },
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{ "cortex-a7", cortex_a7_initfn },
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{ "cortex-a7", cortex_a7_initfn },
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{ "cortex-a8", cortex_a8_initfn },
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{ "cortex-a8", cortex_a8_initfn },
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{ "cortex-a9", cortex_a9_initfn },
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{ "cortex-a9", cortex_a9_initfn },
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