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Arm issue fix. (#738)

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* Fix for MIPS issue.

* Sparc support added.

* M68K support added.

* Arm support ported.

* Fix issue with VS2015 shlobj.h file

* Arm issue fix.
This commit is contained in:
xorstream 2017-01-24 20:45:01 +11:00 committed by Nguyen Anh Quynh
parent 8e45102b43
commit e08d1bf7c6
3 changed files with 11 additions and 14 deletions
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13
qemu/target-arm/cpu.c
View file

@ -685,14 +685,11 @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
* default to 0 and set by private hook * default to 0 and set by private hook
*/ */
{ "A9_PWRCTL", 15,15,0, 0,0,0, 0, { "A9_PWRCTL", 15,15,0, 0,0,0, 0,
0, PL1_RW, NULL, 0, 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c15_power_control) },
offsetof(CPUARMState, cp15.c15_power_control) },
{ "A9_DIAG", 15,15,0, 0,0,1, 0, { "A9_DIAG", 15,15,0, 0,0,1, 0,
0, PL1_RW, NULL, 0, 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c15_diagnostic) },
offsetof(CPUARMState, cp15.c15_diagnostic) },
{ "A9_PWRDIAG",15,15,0, 0,0,2, 0, { "A9_PWRDIAG",15,15,0, 0,0,2, 0,
0, PL1_RW, NULL, 0, 0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c15_power_diagnostic) },
offsetof(CPUARMState, cp15.c15_power_diagnostic) },
{ "NEONBUSY", 15,15,1, 0,0,0, 0, { "NEONBUSY", 15,15,1, 0,0,0, 0,
ARM_CP_CONST, PL1_RW, NULL, 0, }, ARM_CP_CONST, PL1_RW, NULL, 0, },
/* TLB lockdown control */ /* TLB lockdown control */
@ -764,8 +761,8 @@ static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
static const ARMCPRegInfo cortexa15_cp_reginfo[] = { static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
#ifndef CONFIG_USER_ONLY #ifndef CONFIG_USER_ONLY
{ "L2CTLR", 15,9,0, 0,1,2, 0, { "L2CTLR", 15,9,0, 0,1,2, 0,
0, PL1_RW, NULL, 0, 0, NULL, a15_l2ctlr_read, 0, PL1_RW, NULL, 0, 0,
arm_cp_write_ignore, }, NULL, a15_l2ctlr_read, arm_cp_write_ignore, },
#endif #endif
{ "L2ECTLR", 15,9,0, 0,1,3, 0, { "L2ECTLR", 15,9,0, 0,1,3, 0,
ARM_CP_CONST, PL1_RW, NULL, 0 }, ARM_CP_CONST, PL1_RW, NULL, 0 },

2
qemu/target-arm/helper.c
View file

@ -1883,7 +1883,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
ARM_CP_NOP, PL1_W }, ARM_CP_NOP, PL1_W },
{ "ICIALLU", 15,7,5, 0,0,0, 0, { "ICIALLU", 15,7,5, 0,0,0, 0,
ARM_CP_NOP, PL1_W }, ARM_CP_NOP, PL1_W },
{ "ICIMVAU", 15,7,5,0,1, 0, { "ICIMVAU", 15,7,5, 0,0,1, 0,
ARM_CP_NOP, PL1_W }, ARM_CP_NOP, PL1_W },
{ "BPIALL", 15,7,5, 0,0,6, 0, { "BPIALL", 15,7,5, 0,0,6, 0,
ARM_CP_NOP, PL1_W }, ARM_CP_NOP, PL1_W },