yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2024-12-23 00:25:27 +00:00
Code Issues Packages Projects Releases Wiki Activity

Arm issue fix. (#738)

Browse source 
* Fix for MIPS issue.

* Sparc support added.

* M68K support added.

* Arm support ported.

* Fix issue with VS2015 shlobj.h file

* Arm issue fix.
This commit is contained in:
xorstream 2017-01-24 20:45:01 +11:00 committed by Nguyen Anh Quynh
parent 8e45102b43
commit e08d1bf7c6
3 changed files with 11 additions and 14 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

17
qemu/target-arm/cpu.c
View file

@ -635,9 +635,9 @@ static void arm_v7m_class_init(struct uc_struct *uc, ObjectClass *oc, void *data
}
static const ARMCPRegInfo cortexa8_cp_reginfo[] = {
{ "L2LOCKDOWN", 15, 9, 0, 0,1,0, 0,
{ "L2LOCKDOWN", 15,9,0, 0,1,0, 0,
ARM_CP_CONST, PL1_RW, NULL, 0, },
{ "L2AUXCR", 15, 9, 0, 0,1,2, 0,
{ "L2AUXCR", 15,9,0, 0,1,2, 0,
ARM_CP_CONST, PL1_RW, NULL, 0, },
REGINFO_SENTINEL
};
@ -685,14 +685,11 @@ static const ARMCPRegInfo cortexa9_cp_reginfo[] = {
* default to 0 and set by private hook
*/
{ "A9_PWRCTL", 15,15,0, 0,0,0, 0,
0, PL1_RW, NULL, 0,
offsetof(CPUARMState, cp15.c15_power_control) },
0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c15_power_control) },
{ "A9_DIAG", 15,15,0, 0,0,1, 0,
0, PL1_RW, NULL, 0,
offsetof(CPUARMState, cp15.c15_diagnostic) },
0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c15_diagnostic) },
{ "A9_PWRDIAG",15,15,0, 0,0,2, 0,
0, PL1_RW, NULL, 0,
offsetof(CPUARMState, cp15.c15_power_diagnostic) },
0, PL1_RW, NULL, 0, offsetof(CPUARMState, cp15.c15_power_diagnostic) },
{ "NEONBUSY", 15,15,1, 0,0,0, 0,
ARM_CP_CONST, PL1_RW, NULL, 0, },
/* TLB lockdown control */
@ -764,8 +761,8 @@ static uint64_t a15_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
static const ARMCPRegInfo cortexa15_cp_reginfo[] = {
#ifndef CONFIG_USER_ONLY
{ "L2CTLR", 15,9,0, 0,1,2, 0,
0, PL1_RW, NULL, 0, 0, NULL, a15_l2ctlr_read,
arm_cp_write_ignore, },
0, PL1_RW, NULL, 0, 0,
NULL, a15_l2ctlr_read, arm_cp_write_ignore, },
#endif
{ "L2ECTLR", 15,9,0, 0,1,3, 0,
ARM_CP_CONST, PL1_RW, NULL, 0 },

4
qemu/target-arm/cpu64.c
View file

@ -38,10 +38,10 @@ static uint64_t a57_l2ctlr_read(CPUARMState *env, const ARMCPRegInfo *ri)
static const ARMCPRegInfo cortexa57_cp_reginfo[] = {
#ifndef CONFIG_USER_ONLY
{ "L2CTLR_EL1", 0, 11,0, 3,1,2, ARM_CP_STATE_AA64,
{ "L2CTLR_EL1", 0,11,0, 3,1,2, ARM_CP_STATE_AA64,
0, PL1_RW, NULL, 0, 0,
NULL, a57_l2ctlr_read, arm_cp_write_ignore, },
{ "L2CTLR", 15, 9,0, 0,1,2, 0,
{ "L2CTLR", 15,9,0, 0,1,2, 0,
0, PL1_RW, NULL, 0, 0,
NULL, a57_l2ctlr_read, arm_cp_write_ignore, },
#endif

4
qemu/target-arm/helper.c
View file

@ -709,7 +709,7 @@ static const ARMCPRegInfo v7_cp_reginfo[] = {
ARM_CP_NO_MIGRATE, PL0_RW, NULL, 0, offsetoflow32(CPUARMState, cp15.c9_pmcnten),
pmreg_access, NULL, pmcntenclr_write, },
{ "PMCNTENCLR_EL0", 0,9,12, 3,3,2, ARM_CP_STATE_AA64,
ARM_CP_NO_MIGRATE, PL0_RW, NULL, 0,offsetof(CPUARMState, cp15.c9_pmcnten),
ARM_CP_NO_MIGRATE, PL0_RW, NULL, 0, offsetof(CPUARMState, cp15.c9_pmcnten),
pmreg_access, NULL, pmcntenclr_write },
{ "PMOVSR", 15,9,12, 0,0,3, 0,
0, PL0_RW, NULL, 0, offsetof(CPUARMState, cp15.c9_pmovsr),
@ -1883,7 +1883,7 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
ARM_CP_NOP, PL1_W },
{ "ICIALLU", 15,7,5, 0,0,0, 0,
ARM_CP_NOP, PL1_W },
{ "ICIMVAU", 15,7,5,0,1, 0,
{ "ICIMVAU", 15,7,5, 0,0,1, 0,
ARM_CP_NOP, PL1_W },
{ "BPIALL", 15,7,5, 0,0,6, 0,
ARM_CP_NOP, PL1_W },