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https://github.com/yuzu-emu/unicorn.git
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target-arm: Move aarch64_cpu_do_interrupt() to helper.c
Move the aarch64_cpu_do_interrupt() function to helper.c. We want to be able to call this from code that isn't AArch64-only, and the move allows us to avoid awkward #ifdeffery at the callsite. Backports commit f3a9b6945cbbb23f3a70da14e9ffdf1e60c580a8 from qemu
This commit is contained in:
Peter Maydell
Lioncash
parent
c06519a2fd
commit
e1925bb5fb
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@ -243,8 +243,8 @@ void arm_gt_stimer_cb(void *opaque);
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#ifdef TARGET_AARCH64
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int aarch64_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg);
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int aarch64_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg);
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#endif
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void aarch64_cpu_do_interrupt(CPUState *cs);
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#endif
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#endif
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@ -512,100 +512,3 @@ uint64_t HELPER(crc32c_64)(uint64_t acc, uint64_t val, uint32_t bytes)
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/* Linux crc32c converts the output to one's complement. */
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return crc32c(acc, buf, bytes) ^ 0xffffffff;
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}
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#if !defined(CONFIG_USER_ONLY)
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/* Handle a CPU exception. */
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void aarch64_cpu_do_interrupt(CPUState *cs)
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{
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CPUARMState *env = cs->env_ptr;
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ARMCPU *cpu = ARM_CPU(env->uc, cs);
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unsigned int new_el = env->exception.target_el;
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target_ulong addr = env->cp15.vbar_el[new_el];
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unsigned int new_mode = aarch64_pstate_mode(new_el, true);
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if (arm_current_el(env) < new_el) {
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if (env->aarch64) {
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addr += 0x400;
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} else {
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addr += 0x600;
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}
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} else if (pstate_read(env) & PSTATE_SP) {
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addr += 0x200;
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}
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arm_log_exception(cs->exception_index);
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qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env),
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new_el);
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if (qemu_loglevel_mask(CPU_LOG_INT)
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&& !excp_is_internal(cs->exception_index)) {
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qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%" PRIx32 "\n",
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env->exception.syndrome);
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}
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if (arm_is_psci_call(cpu, cs->exception_index)) {
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arm_handle_psci_call(cpu);
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qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
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return;
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}
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switch (cs->exception_index) {
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case EXCP_PREFETCH_ABORT:
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case EXCP_DATA_ABORT:
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env->cp15.far_el[new_el] = env->exception.vaddress;
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qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n",
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env->cp15.far_el[new_el]);
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/* fall through */
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case EXCP_BKPT:
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case EXCP_UDEF:
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case EXCP_SWI:
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case EXCP_HVC:
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case EXCP_HYP_TRAP:
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case EXCP_SMC:
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env->cp15.esr_el[new_el] = env->exception.syndrome;
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break;
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case EXCP_IRQ:
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case EXCP_VIRQ:
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addr += 0x80;
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break;
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case EXCP_FIQ:
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case EXCP_VFIQ:
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addr += 0x100;
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break;
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case EXCP_SEMIHOST:
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/* UNICORN: Commented out
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qemu_log_mask(CPU_LOG_INT,
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"...handling as semihosting call 0x%" PRIx64 "\n",
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env->xregs[0]);
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env->xregs[0] = do_arm_semihosting(env);*/
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return;
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default:
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cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
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}
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if (is_a64(env)) {
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env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env);
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aarch64_save_sp(env, arm_current_el(env));
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env->elr_el[new_el] = env->pc;
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} else {
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env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env);
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if (!env->thumb) {
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env->cp15.esr_el[new_el] |= 1 << 25;
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}
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env->elr_el[new_el] = env->regs[15];
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aarch64_sync_32_to_64(env);
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env->condexec_bits = 0;
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}
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qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
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env->elr_el[new_el]);
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pstate_write(env, PSTATE_DAIF | new_mode);
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env->aarch64 = 1;
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aarch64_restore_sp(env, new_el);
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env->pc = addr;
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cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
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}
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#endif
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@ -5245,6 +5245,100 @@ void arm_cpu_do_interrupt(CPUState *cs)
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cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
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}
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/* Handle a CPU exception. */
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void aarch64_cpu_do_interrupt(CPUState *cs)
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{
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CPUARMState *env = cs->env_ptr;
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ARMCPU *cpu = ARM_CPU(env->uc, cs);
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unsigned int new_el = env->exception.target_el;
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target_ulong addr = env->cp15.vbar_el[new_el];
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unsigned int new_mode = aarch64_pstate_mode(new_el, true);
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if (arm_current_el(env) < new_el) {
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if (env->aarch64) {
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addr += 0x400;
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} else {
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addr += 0x600;
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}
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} else if (pstate_read(env) & PSTATE_SP) {
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addr += 0x200;
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}
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arm_log_exception(cs->exception_index);
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qemu_log_mask(CPU_LOG_INT, "...from EL%d to EL%d\n", arm_current_el(env),
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new_el);
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if (qemu_loglevel_mask(CPU_LOG_INT)
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&& !excp_is_internal(cs->exception_index)) {
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qemu_log_mask(CPU_LOG_INT, "...with ESR 0x%" PRIx32 "\n",
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env->exception.syndrome);
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}
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if (arm_is_psci_call(cpu, cs->exception_index)) {
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arm_handle_psci_call(cpu);
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qemu_log_mask(CPU_LOG_INT, "...handled as PSCI call\n");
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return;
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}
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switch (cs->exception_index) {
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case EXCP_PREFETCH_ABORT:
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case EXCP_DATA_ABORT:
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env->cp15.far_el[new_el] = env->exception.vaddress;
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qemu_log_mask(CPU_LOG_INT, "...with FAR 0x%" PRIx64 "\n",
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env->cp15.far_el[new_el]);
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/* fall through */
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case EXCP_BKPT:
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case EXCP_UDEF:
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case EXCP_SWI:
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case EXCP_HVC:
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case EXCP_HYP_TRAP:
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case EXCP_SMC:
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env->cp15.esr_el[new_el] = env->exception.syndrome;
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break;
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case EXCP_IRQ:
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case EXCP_VIRQ:
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addr += 0x80;
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break;
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case EXCP_FIQ:
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case EXCP_VFIQ:
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addr += 0x100;
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break;
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case EXCP_SEMIHOST:
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/* UNICORN: Commented out
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qemu_log_mask(CPU_LOG_INT,
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"...handling as semihosting call 0x%" PRIx64 "\n",
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env->xregs[0]);
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env->xregs[0] = do_arm_semihosting(env);*/
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return;
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default:
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cpu_abort(cs, "Unhandled exception 0x%x\n", cs->exception_index);
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}
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if (is_a64(env)) {
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env->banked_spsr[aarch64_banked_spsr_index(new_el)] = pstate_read(env);
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aarch64_save_sp(env, arm_current_el(env));
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env->elr_el[new_el] = env->pc;
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} else {
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env->banked_spsr[aarch64_banked_spsr_index(new_el)] = cpsr_read(env);
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if (!env->thumb) {
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env->cp15.esr_el[new_el] |= 1 << 25;
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}
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env->elr_el[new_el] = env->regs[15];
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aarch64_sync_32_to_64(env);
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env->condexec_bits = 0;
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}
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qemu_log_mask(CPU_LOG_INT, "...with ELR 0x%" PRIx64 "\n",
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env->elr_el[new_el]);
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pstate_write(env, PSTATE_DAIF | new_mode);
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env->aarch64 = 1;
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aarch64_restore_sp(env, new_el);
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env->pc = addr;
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cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
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}
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/* Return the exception level which controls this address translation regime */
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static inline uint32_t regime_el(CPUARMState *env, ARMMMUIdx mmu_idx)
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{
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