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tcg/arm: Add support for fence

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Backports commit 40f191ab8226fdada185efa49c44b60d8f494890 from qemu
This commit is contained in:
Pranith Kumar 2018-02-26 03:13:12 -05:00 committed by Lioncash
parent 907060b865
commit e29cbe9640
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 17 additions and 0 deletions
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17
qemu/tcg/arm/tcg-target.inc.c
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@ -313,6 +313,9 @@ typedef enum {
INSN_LDRD_REG = 0x000000d0,
INSN_STRD_IMM = 0x004000f0,
INSN_STRD_REG = 0x000000f0,
INSN_DMB_ISH = 0x5bf07ff5,
INSN_DMB_MCR = 0xba0f07ee,
} ARMInsn;
#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
@ -1066,6 +1069,15 @@ static inline void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l)
}
}
static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
{
if (use_armv7_instructions) {
tcg_out32(s, INSN_DMB_ISH);
} else if (use_armv6_instructions) {
tcg_out32(s, INSN_DMB_MCR);
}
}
#ifdef CONFIG_SOFTMMU
/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
* int mmu_idx, uintptr_t ra)
@ -1928,6 +1940,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]);
break;
case INDEX_op_mb:
tcg_out_mb(s, args[0]);
break;
case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
case INDEX_op_call: /* Always emitted via tcg_out_call. */
@ -2002,6 +2018,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
{ INDEX_op_div_i32, { "r", "r", "r" } },
{ INDEX_op_divu_i32, { "r", "r", "r" } },
{ INDEX_op_mb, { } },
{ -1 },
};