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tcg/arm: Add support for fence
Backports commit 40f191ab8226fdada185efa49c44b60d8f494890 from qemu
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@ -313,6 +313,9 @@ typedef enum {
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INSN_LDRD_REG = 0x000000d0,
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INSN_STRD_IMM = 0x004000f0,
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INSN_STRD_REG = 0x000000f0,
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INSN_DMB_ISH = 0x5bf07ff5,
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INSN_DMB_MCR = 0xba0f07ee,
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} ARMInsn;
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#define SHIFT_IMM_LSL(im) (((im) << 7) | 0x00)
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@ -1066,6 +1069,15 @@ static inline void tcg_out_goto_label(TCGContext *s, int cond, TCGLabel *l)
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}
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}
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static inline void tcg_out_mb(TCGContext *s, TCGArg a0)
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{
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if (use_armv7_instructions) {
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tcg_out32(s, INSN_DMB_ISH);
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} else if (use_armv6_instructions) {
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tcg_out32(s, INSN_DMB_MCR);
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}
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}
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#ifdef CONFIG_SOFTMMU
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/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr,
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* int mmu_idx, uintptr_t ra)
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@ -1928,6 +1940,10 @@ static inline void tcg_out_op(TCGContext *s, TCGOpcode opc,
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tcg_out_udiv(s, COND_AL, args[0], args[1], args[2]);
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break;
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case INDEX_op_mb:
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tcg_out_mb(s, args[0]);
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break;
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case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */
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case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */
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case INDEX_op_call: /* Always emitted via tcg_out_call. */
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@ -2002,6 +2018,7 @@ static const TCGTargetOpDef arm_op_defs[] = {
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{ INDEX_op_div_i32, { "r", "r", "r" } },
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{ INDEX_op_divu_i32, { "r", "r", "r" } },
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{ INDEX_op_mb, { } },
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{ -1 },
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};
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