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target/arm: Convert Neon 3-reg-same SHA to decodetree

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Convert the Neon SHA instructions in the 3-reg-same group
to decodetree

Backports commit 21290edfc29d8929741c0ed043733c23c69bc3b9 from qemu
This commit is contained in:
Peter Maydell 2020-05-15 22:34:12 -04:00 committed by Lioncash
parent 1740e018f4
commit e2b703a82c
3 changed files with 155 additions and 44 deletions
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10
qemu/target/arm/neon-dp.decode
View file

@ -99,4 +99,14 @@ VMUL_3s 1111 001 0 0 . .. .... .... 1001 . . . 1 .... @3same
VMUL_p_3s 1111 001 1 0 . .. .... .... 1001 . . . 1 .... @3same
VQRDMLAH_3s 1111 001 1 0 . .. .... .... 1011 ... 1 .... @3same
SHA1_3s 1111 001 0 0 . optype:2 .... .... 1100 . 1 . 0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp
SHA256H_3s 1111 001 1 0 . 00 .... .... 1100 . 1 . 0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp
SHA256H2_3s 1111 001 1 0 . 01 .... .... 1100 . 1 . 0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp
SHA256SU1_3s 1111 001 1 0 . 10 .... .... 1100 . 1 . 0 .... \
vm=%vm_dp vn=%vn_dp vd=%vd_dp
VQRDMLSH_3s 1111 001 1 0 . .. .... .... 1100 ... 1 .... @3same

143
qemu/target/arm/translate-neon.inc.c
View file

@ -699,3 +699,146 @@ static bool trans_VMUL_p_3s(DisasContext *s, arg_3same *a)
DO_VQRDMLAH(VQRDMLAH, gen_gvec_sqrdmlah_qc)
DO_VQRDMLAH(VQRDMLSH, gen_gvec_sqrdmlsh_qc)
static bool trans_SHA1_3s(DisasContext *s, arg_SHA1_3s *a)
{
TCGv_ptr ptr1, ptr2, ptr3;
TCGv_i32 tmp;
TCGContext *tcg_ctx = s->uc->tcg_ctx;
if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
!dc_isar_feature(aa32_sha1, s)) {
return false;
}
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) &&
((a->vd | a->vn | a->vm) & 0x10)) {
return false;
}
if ((a->vn | a->vm | a->vd) & 1) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
ptr1 = vfp_reg_ptr(s, true, a->vd);
ptr2 = vfp_reg_ptr(s, true, a->vn);
ptr3 = vfp_reg_ptr(s, true, a->vm);
tmp = tcg_const_i32(tcg_ctx, a->optype);
gen_helper_crypto_sha1_3reg(tcg_ctx, ptr1, ptr2, ptr3, tmp);
tcg_temp_free_i32(tcg_ctx, tmp);
tcg_temp_free_ptr(tcg_ctx, ptr1);
tcg_temp_free_ptr(tcg_ctx, ptr2);
tcg_temp_free_ptr(tcg_ctx, ptr3);
return true;
}
static bool trans_SHA256H_3s(DisasContext *s, arg_SHA256H_3s *a)
{
TCGv_ptr ptr1, ptr2, ptr3;
TCGContext *tcg_ctx = s->uc->tcg_ctx;
if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
!dc_isar_feature(aa32_sha2, s)) {
return false;
}
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) &&
((a->vd | a->vn | a->vm) & 0x10)) {
return false;
}
if ((a->vn | a->vm | a->vd) & 1) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
ptr1 = vfp_reg_ptr(s, true, a->vd);
ptr2 = vfp_reg_ptr(s, true, a->vn);
ptr3 = vfp_reg_ptr(s, true, a->vm);
gen_helper_crypto_sha256h(tcg_ctx, ptr1, ptr2, ptr3);
tcg_temp_free_ptr(tcg_ctx, ptr1);
tcg_temp_free_ptr(tcg_ctx, ptr2);
tcg_temp_free_ptr(tcg_ctx, ptr3);
return true;
}
static bool trans_SHA256H2_3s(DisasContext *s, arg_SHA256H2_3s *a)
{
TCGv_ptr ptr1, ptr2, ptr3;
TCGContext *tcg_ctx = s->uc->tcg_ctx;
if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
!dc_isar_feature(aa32_sha2, s)) {
return false;
}
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) &&
((a->vd | a->vn | a->vm) & 0x10)) {
return false;
}
if ((a->vn | a->vm | a->vd) & 1) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
ptr1 = vfp_reg_ptr(s, true, a->vd);
ptr2 = vfp_reg_ptr(s, true, a->vn);
ptr3 = vfp_reg_ptr(s, true, a->vm);
gen_helper_crypto_sha256h2(tcg_ctx, ptr1, ptr2, ptr3);
tcg_temp_free_ptr(tcg_ctx, ptr1);
tcg_temp_free_ptr(tcg_ctx, ptr2);
tcg_temp_free_ptr(tcg_ctx, ptr3);
return true;
}
static bool trans_SHA256SU1_3s(DisasContext *s, arg_SHA256SU1_3s *a)
{
TCGv_ptr ptr1, ptr2, ptr3;
TCGContext *tcg_ctx = s->uc->tcg_ctx;
if (!arm_dc_feature(s, ARM_FEATURE_NEON) ||
!dc_isar_feature(aa32_sha2, s)) {
return false;
}
/* UNDEF accesses to D16-D31 if they don't exist. */
if (!dc_isar_feature(aa32_simd_r32, s) &&
((a->vd | a->vn | a->vm) & 0x10)) {
return false;
}
if ((a->vn | a->vm | a->vd) & 1) {
return false;
}
if (!vfp_access_check(s)) {
return true;
}
ptr1 = vfp_reg_ptr(s, true, a->vd);
ptr2 = vfp_reg_ptr(s, true, a->vn);
ptr3 = vfp_reg_ptr(s, true, a->vm);
gen_helper_crypto_sha256su1(tcg_ctx, ptr1, ptr2, ptr3);
tcg_temp_free_ptr(tcg_ctx, ptr1);
tcg_temp_free_ptr(tcg_ctx, ptr2);
tcg_temp_free_ptr(tcg_ctx, ptr3);
return true;
}

46
qemu/target/arm/translate.c
View file

@ -5486,7 +5486,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
int vec_size;
uint32_t imm;
TCGv_i32 tmp, tmp2, tmp3, tmp4, tmp5;
TCGv_ptr ptr1, ptr2, ptr3;
TCGv_ptr ptr1, ptr2;
TCGv_i64 tmp64;
if (!arm_dc_feature(s, ARM_FEATURE_NEON)) {
@ -5530,49 +5530,6 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
return 1;
}
switch (op) {
case NEON_3R_SHA:
/* The SHA-1/SHA-256 3-register instructions require special
* treatment here, as their size field is overloaded as an
* op type selector, and they all consume their input in a
* single pass.
*/
if (!q) {
return 1;
}
if (!u) { /* SHA-1 */
if (!dc_isar_feature(aa32_sha1, s)) {
return 1;
}
ptr1 = vfp_reg_ptr(s, true, rd);
ptr2 = vfp_reg_ptr(s, true, rn);
ptr3 = vfp_reg_ptr(s, true, rm);
tmp4 = tcg_const_i32(tcg_ctx, size);
gen_helper_crypto_sha1_3reg(tcg_ctx, ptr1, ptr2, ptr3, tmp4);
tcg_temp_free_i32(tcg_ctx, tmp4);
} else { /* SHA-256 */
if (!dc_isar_feature(aa32_sha2, s) || size == 3) {
return 1;
}
ptr1 = vfp_reg_ptr(s, true, rd);
ptr2 = vfp_reg_ptr(s, true, rn);
ptr3 = vfp_reg_ptr(s, true, rm);
switch (size) {
case 0:
gen_helper_crypto_sha256h(tcg_ctx, ptr1, ptr2, ptr3);
break;
case 1:
gen_helper_crypto_sha256h2(tcg_ctx, ptr1, ptr2, ptr3);
break;
case 2:
gen_helper_crypto_sha256su1(tcg_ctx, ptr1, ptr2, ptr3);
break;
}
}
tcg_temp_free_ptr(tcg_ctx, ptr1);
tcg_temp_free_ptr(tcg_ctx, ptr2);
tcg_temp_free_ptr(tcg_ctx, ptr3);
return 0;
case NEON_3R_VPADD_VQRDMLAH:
if (!u) {
break; /* VPADD */
@ -5623,6 +5580,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn)
case NEON_3R_VMUL:
case NEON_3R_VML:
case NEON_3R_VSHL:
case NEON_3R_SHA:
/* Already handled by decodetree */
return 1;
}