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tcg: Drop union from TCGArgConstraint

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The union is unused; let "regs" appear in the main structure
without the "u.regs" wrapping.

Backports 9be0d08019465b38e2f1a605960961a491430c21
This commit is contained in:
Richard Henderson 2021-03-01 19:29:18 -05:00 committed by Lioncash
parent 1551f6be9d
commit e3356f9bad
9 changed files with 81 additions and 83 deletions
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14
qemu/tcg/aarch64/tcg-target.inc.c
View file

@ -129,22 +129,22 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
switch (*ct_str++) { switch (*ct_str++) {
case 'r': /* general registers */ case 'r': /* general registers */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs |= 0xffffffffu; ct->regs |= 0xffffffffu;
break; break;
case 'w': /* advsimd registers */ case 'w': /* advsimd registers */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs |= 0xffffffff00000000ull; ct->regs |= 0xffffffff00000000ull;
break; break;
case 'l': /* qemu_ld / qemu_st address, data_reg */ case 'l': /* qemu_ld / qemu_st address, data_reg */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffffffffu; ct->regs = 0xffffffffu;
#ifdef CONFIG_SOFTMMU #ifdef CONFIG_SOFTMMU
/* x0 and x1 will be overwritten when reading the tlb entry, /* x0 and x1 will be overwritten when reading the tlb entry,
and x2, and x3 for helper args, better to avoid using them. */ and x2, and x3 for helper args, better to avoid using them. */
tcg_regset_reset_reg(ct->u.regs, TCG_REG_X0); tcg_regset_reset_reg(ct->regs, TCG_REG_X0);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_X1); tcg_regset_reset_reg(ct->regs, TCG_REG_X1);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_X2); tcg_regset_reset_reg(ct->regs, TCG_REG_X2);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_X3); tcg_regset_reset_reg(ct->regs, TCG_REG_X3);
#endif #endif
break; break;
case 'A': /* Valid for arithmetic immediate (positive or negative). */ case 'A': /* Valid for arithmetic immediate (positive or negative). */

24
qemu/tcg/arm/tcg-target.inc.c
View file

@ -254,39 +254,39 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
case 'r': case 'r':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffff; ct->regs = 0xffff;
break; break;
/* qemu_ld address */ /* qemu_ld address */
case 'l': case 'l':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffff; ct->regs = 0xffff;
#ifdef CONFIG_SOFTMMU #ifdef CONFIG_SOFTMMU
/* r0-r2,lr will be overwritten when reading the tlb entry, /* r0-r2,lr will be overwritten when reading the tlb entry,
so don't use these. */ so don't use these. */
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14); tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
#endif #endif
break; break;
/* qemu_st address & data */ /* qemu_st address & data */
case 's': case 's':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffff; ct->regs = 0xffff;
/* r0-r2 will be overwritten when reading the tlb entry (softmmu only) /* r0-r2 will be overwritten when reading the tlb entry (softmmu only)
and r0-r1 doing the byte swapping, so don't use these. */ and r0-r1 doing the byte swapping, so don't use these. */
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R0); tcg_regset_reset_reg(ct->regs, TCG_REG_R0);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R1); tcg_regset_reset_reg(ct->regs, TCG_REG_R1);
#if defined(CONFIG_SOFTMMU) #if defined(CONFIG_SOFTMMU)
/* Avoid clashes with registers being used for helper args */ /* Avoid clashes with registers being used for helper args */
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
#if TARGET_LONG_BITS == 64 #if TARGET_LONG_BITS == 64
/* Avoid clashes with registers being used for helper args */ /* Avoid clashes with registers being used for helper args */
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
#endif #endif
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R14); tcg_regset_reset_reg(ct->regs, TCG_REG_R14);
#endif #endif
break; break;

26
qemu/tcg/i386/tcg-target.inc.c
View file

@ -216,42 +216,42 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
switch(*ct_str++) { switch(*ct_str++) {
case 'a': case 'a':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->u.regs, TCG_REG_EAX); tcg_regset_set_reg(ct->regs, TCG_REG_EAX);
break; break;
case 'b': case 'b':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->u.regs, TCG_REG_EBX); tcg_regset_set_reg(ct->regs, TCG_REG_EBX);
break; break;
case 'c': case 'c':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->u.regs, TCG_REG_ECX); tcg_regset_set_reg(ct->regs, TCG_REG_ECX);
break; break;
case 'd': case 'd':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->u.regs, TCG_REG_EDX); tcg_regset_set_reg(ct->regs, TCG_REG_EDX);
break; break;
case 'S': case 'S':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->u.regs, TCG_REG_ESI); tcg_regset_set_reg(ct->regs, TCG_REG_ESI);
break; break;
case 'D': case 'D':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->u.regs, TCG_REG_EDI); tcg_regset_set_reg(ct->regs, TCG_REG_EDI);
break; break;
case 'q': case 'q':
/* A register that can be used as a byte operand. */ /* A register that can be used as a byte operand. */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf; ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xf;
break; break;
case 'Q': case 'Q':
/* A register with an addressable second byte (e.g. %ah). */ /* A register with an addressable second byte (e.g. %ah). */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs = 0xf; ct->regs = 0xf;
break; break;
case 'r': case 'r':
/* A general register. */ /* A general register. */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs |= ALL_GENERAL_REGS; ct->regs |= ALL_GENERAL_REGS;
break; break;
case 'W': case 'W':
/* With TZCNT/LZCNT, we can have operand-size as an input. */ /* With TZCNT/LZCNT, we can have operand-size as an input. */
@ -260,15 +260,15 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
case 'x': case 'x':
/* A vector register. */ /* A vector register. */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs |= ALL_VECTOR_REGS; ct->regs |= ALL_VECTOR_REGS;
break; break;
/* qemu_ld/st address constraint */ /* qemu_ld/st address constraint */
case 'L': case 'L':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff; ct->regs = TCG_TARGET_REG_BITS == 64 ? 0xffff : 0xff;
tcg_regset_reset_reg(ct->u.regs, TCG_REG_L0); tcg_regset_reset_reg(ct->regs, TCG_REG_L0);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_L1); tcg_regset_reset_reg(ct->regs, TCG_REG_L1);
break; break;
case 'e': case 'e':

18
qemu/tcg/mips/tcg-target.inc.c
View file

@ -196,28 +196,28 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
switch(*ct_str++) { switch(*ct_str++) {
case 'r': case 'r':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffffffff; ct->regs = 0xffffffff;
break; break;
case 'L': /* qemu_ld input arg constraint */ case 'L': /* qemu_ld input arg constraint */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffffffff; ct->regs = 0xffffffff;
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0); tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
#if defined(CONFIG_SOFTMMU) #if defined(CONFIG_SOFTMMU)
if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2); tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
} }
#endif #endif
break; break;
case 'S': /* qemu_st constraint */ case 'S': /* qemu_st constraint */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffffffff; ct->regs = 0xffffffff;
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A0); tcg_regset_reset_reg(ct->regs, TCG_REG_A0);
#if defined(CONFIG_SOFTMMU) #if defined(CONFIG_SOFTMMU)
if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) {
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A2); tcg_regset_reset_reg(ct->regs, TCG_REG_A2);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A3); tcg_regset_reset_reg(ct->regs, TCG_REG_A3);
} else { } else {
tcg_regset_reset_reg(ct->u.regs, TCG_REG_A1); tcg_regset_reset_reg(ct->regs, TCG_REG_A1);
} }
#endif #endif
break; break;

22
qemu/tcg/ppc/tcg-target.inc.c
View file

@ -227,29 +227,29 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
switch (*ct_str++) { switch (*ct_str++) {
case 'A': case 'B': case 'C': case 'D': case 'A': case 'B': case 'C': case 'D':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
tcg_regset_set_reg(ct->u.regs, 3 + ct_str[0] - 'A'); tcg_regset_set_reg(ct->regs, 3 + ct_str[0] - 'A');
break; break;
case 'r': case 'r':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffffffff; ct->regs = 0xffffffff;
break; break;
case 'L': /* qemu_ld constraint */ case 'L': /* qemu_ld constraint */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffffffff; ct->regs = 0xffffffff;
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
#ifdef CONFIG_SOFTMMU #ifdef CONFIG_SOFTMMU
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
#endif #endif
break; break;
case 'S': /* qemu_st constraint */ case 'S': /* qemu_st constraint */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffffffff; ct->regs = 0xffffffff;
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
#ifdef CONFIG_SOFTMMU #ifdef CONFIG_SOFTMMU
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R5); tcg_regset_reset_reg(ct->regs, TCG_REG_R5);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R6); tcg_regset_reset_reg(ct->regs, TCG_REG_R6);
#endif #endif
break; break;
case 'I': case 'I':

18
qemu/tcg/s390/tcg-target.inc.c
View file

@ -415,24 +415,24 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
switch (*ct_str++) { switch (*ct_str++) {
case 'r': /* all registers */ case 'r': /* all registers */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffff; ct->regs = 0xffff;
break; break;
case 'L': /* qemu_ld/st constraint */ case 'L': /* qemu_ld/st constraint */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffff; ct->regs = 0xffff;
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R2); tcg_regset_reset_reg(ct->regs, TCG_REG_R2);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R3); tcg_regset_reset_reg(ct->regs, TCG_REG_R3);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_R4); tcg_regset_reset_reg(ct->regs, TCG_REG_R4);
break; break;
case 'a': /* force R2 for division */ case 'a': /* force R2 for division */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs = 0; ct->regs = 0;
tcg_regset_set_reg(ct->u.regs, TCG_REG_R2); tcg_regset_set_reg(ct->regs, TCG_REG_R2);
break; break;
case 'b': /* force R3 for division */ case 'b': /* force R3 for division */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs = 0; ct->regs = 0;
tcg_regset_set_reg(ct->u.regs, TCG_REG_R3); tcg_regset_set_reg(ct->regs, TCG_REG_R3);
break; break;
case 'A': case 'A':
ct->ct |= TCG_CT_CONST_S33; ct->ct |= TCG_CT_CONST_S33;

16
qemu/tcg/sparc/tcg-target.inc.c
View file

@ -329,27 +329,27 @@ static const char *target_parse_constraint(TCGArgConstraint *ct,
switch (*ct_str++) { switch (*ct_str++) {
case 'r': case 'r':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffffffff; ct->regs = 0xffffffff;
break; break;
case 'R': case 'R':
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs = ALL_64; ct->regs = ALL_64;
break; break;
case 'A': /* qemu_ld/st address constraint */ case 'A': /* qemu_ld/st address constraint */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff; ct->regs = TARGET_LONG_BITS == 64 ? ALL_64 : 0xffffffff;
reserve_helpers: reserve_helpers:
tcg_regset_reset_reg(ct->u.regs, TCG_REG_O0); tcg_regset_reset_reg(ct->regs, TCG_REG_O0);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_O1); tcg_regset_reset_reg(ct->regs, TCG_REG_O1);
tcg_regset_reset_reg(ct->u.regs, TCG_REG_O2); tcg_regset_reset_reg(ct->regs, TCG_REG_O2);
break; break;
case 's': /* qemu_st data 32-bit constraint */ case 's': /* qemu_st data 32-bit constraint */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs = 0xffffffff; ct->regs = 0xffffffff;
goto reserve_helpers; goto reserve_helpers;
case 'S': /* qemu_st data 64-bit constraint */ case 'S': /* qemu_st data 64-bit constraint */
ct->ct |= TCG_CT_REG; ct->ct |= TCG_CT_REG;
ct->u.regs = ALL_64; ct->regs = ALL_64;
goto reserve_helpers; goto reserve_helpers;
case 'I': case 'I':
ct->ct |= TCG_CT_CONST_S11; ct->ct |= TCG_CT_CONST_S11;

22
qemu/tcg/tcg.c
View file

@ -1603,7 +1603,7 @@ static int get_constraint_priority(const TCGOpDef *def, int k)
return 0; return 0;
n = 0; n = 0;
for(i = 0; i < TCG_TARGET_NB_REGS; i++) { for(i = 0; i < TCG_TARGET_NB_REGS; i++) {
if (tcg_regset_test_reg(arg_ct->u.regs, i)) if (tcg_regset_test_reg(arg_ct->regs, i))
n++; n++;
} }
} }
@ -1661,7 +1661,7 @@ static void process_op_defs(TCGContext *s)
/* Incomplete TCGTargetOpDef entry. */ /* Incomplete TCGTargetOpDef entry. */
tcg_debug_assert(ct_str != NULL); tcg_debug_assert(ct_str != NULL);
def->args_ct[i].u.regs = 0; def->args_ct[i].regs = 0;
def->args_ct[i].ct = 0; def->args_ct[i].ct = 0;
while (*ct_str != '\0') { while (*ct_str != '\0') {
switch(*ct_str) { switch(*ct_str) {
@ -2284,13 +2284,13 @@ static void liveness_pass_1(TCGContext *s)
pset = la_temp_pref(ts); pset = la_temp_pref(ts);
set = *pset; set = *pset;
set &= ct->u.regs; set &= ct->regs;
if (ct->ct & TCG_CT_IALIAS) { if (ct->ct & TCG_CT_IALIAS) {
set &= op->output_pref[ct->alias_index]; set &= op->output_pref[ct->alias_index];
} }
/* If the combination is not possible, restart. */ /* If the combination is not possible, restart. */
if (set == 0) { if (set == 0) {
set = ct->u.regs; set = ct->regs;
} }
*pset = set; *pset = set;
} }
@ -2980,8 +2980,8 @@ static void tcg_reg_alloc_dup(TCGContext *s, const TCGOp *op)
return; return;
} }
dup_out_regs = s->tcg_op_defs[INDEX_op_dup_vec].args_ct[0].u.regs; dup_out_regs = s->tcg_op_defs[INDEX_op_dup_vec].args_ct[0].regs;
dup_in_regs = s->tcg_op_defs[INDEX_op_dup_vec].args_ct[1].u.regs; dup_in_regs = s->tcg_op_defs[INDEX_op_dup_vec].args_ct[1].regs;
/* Allocate the output register now. */ /* Allocate the output register now. */
if (ots->val_type != TEMP_VAL_REG) { if (ots->val_type != TEMP_VAL_REG) {
@ -3135,10 +3135,10 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
} }
} }
temp_load(s, ts, arg_ct->u.regs, i_allocated_regs, i_preferred_regs); temp_load(s, ts, arg_ct->regs, i_allocated_regs, i_preferred_regs);
reg = ts->reg; reg = ts->reg;
if (tcg_regset_test_reg(arg_ct->u.regs, reg)) { if (tcg_regset_test_reg(arg_ct->regs, reg)) {
/* nothing to do : the constraint is satisfied */ /* nothing to do : the constraint is satisfied */
} else { } else {
allocate_in_reg: allocate_in_reg:
@ -3146,7 +3146,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
and move the temporary register into it */ and move the temporary register into it */
temp_load(s, ts, s->tcg_target_available_regs[ts->type], temp_load(s, ts, s->tcg_target_available_regs[ts->type],
i_allocated_regs, 0); i_allocated_regs, 0);
reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs, reg = tcg_reg_alloc(s, arg_ct->regs, i_allocated_regs,
o_preferred_regs, ts->indirect_base); o_preferred_regs, ts->indirect_base);
if (!tcg_out_mov(s, ts->type, reg, ts->reg)) { if (!tcg_out_mov(s, ts->type, reg, ts->reg)) {
/* /*
@ -3201,11 +3201,11 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op)
&& !const_args[arg_ct->alias_index]) { && !const_args[arg_ct->alias_index]) {
reg = new_args[arg_ct->alias_index]; reg = new_args[arg_ct->alias_index];
} else if (arg_ct->ct & TCG_CT_NEWREG) { } else if (arg_ct->ct & TCG_CT_NEWREG) {
reg = tcg_reg_alloc(s, arg_ct->u.regs, reg = tcg_reg_alloc(s, arg_ct->regs,
i_allocated_regs | o_allocated_regs, i_allocated_regs | o_allocated_regs,
op->output_pref[k], ts->indirect_base); op->output_pref[k], ts->indirect_base);
} else { } else {
reg = tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs, reg = tcg_reg_alloc(s, arg_ct->regs, o_allocated_regs,
op->output_pref[k], ts->indirect_base); op->output_pref[k], ts->indirect_base);
} }
tcg_regset_set_reg(o_allocated_regs, reg); tcg_regset_set_reg(o_allocated_regs, reg);

4
qemu/tcg/tcg.h
View file

@ -627,9 +627,7 @@ void tcg_dump_info(void);
typedef struct TCGArgConstraint { typedef struct TCGArgConstraint {
uint16_t ct; uint16_t ct;
uint8_t alias_index; uint8_t alias_index;
union { TCGRegSet regs;
TCGRegSet regs;
} u;
} TCGArgConstraint; } TCGArgConstraint;
#define TCG_MAX_OP_ARGS 16 #define TCG_MAX_OP_ARGS 16