yuzu/unicorn
1
0
Fork 0
mirror of https://github.com/yuzu-emu/unicorn.git synced 2025-01-10 20:35:36 +00:00
Code Issues Packages Projects Releases Wiki Activity

target-i386: Remove redundant HF_SOFTMMU_MASK

Browse source 
'HF_SOFTMMU_MASK' is only set when 'CONFIG_SOFTMMU' is defined. So
there's no need in this flag: test 'CONFIG_SOFTMMU' instead.

Backports commit da6d48e3348bbc266896cf8adf0c33f1eaf5b31f from qemu
This commit is contained in:
Sergey Fedorov 2018-02-25 19:49:55 -05:00 committed by Lioncash
parent 4a904baaf5
commit e39b9d0391
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
3 changed files with 5 additions and 15 deletions
Show stats Download patch file Download diff file Expand all files Collapse all files

3
qemu/target-i386/cpu.c
View file

@ -2820,9 +2820,6 @@ static void x86_cpu_reset(CPUState *s)
/* init to reset state */
#ifdef CONFIG_SOFTMMU
env->hflags |= HF_SOFTMMU_MASK;
#endif
env->hflags2 |= HF2_GIF_MASK;
cpu_x86_update_cr0(env, 0x60000010);

5
qemu/target-i386/cpu.h
View file

@ -11,7 +11,7 @@
* This library is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* Lesser General Public License for more details.
* Lesser General Publifc License for more details.
*
* You should have received a copy of the GNU Lesser General Public
* License along with this library; if not, see <http://www.gnu.org/licenses/>.
@ -130,8 +130,6 @@
positions to ease oring with eflags. */
/* current cpl */
#define HF_CPL_SHIFT 0
/* true if soft mmu is being used */
#define HF_SOFTMMU_SHIFT 2
/* true if hardware interrupts must be disabled for next instruction */
#define HF_INHIBIT_IRQ_SHIFT 3
/* 16 or 32 segments */
@ -161,7 +159,6 @@
#define HF_MPX_IU_SHIFT 26 /* BND registers in-use */
#define HF_CPL_MASK (3 << HF_CPL_SHIFT)
#define HF_SOFTMMU_MASK (1 << HF_SOFTMMU_SHIFT)
#define HF_INHIBIT_IRQ_MASK (1 << HF_INHIBIT_IRQ_SHIFT)
#define HF_CS32_MASK (1 << HF_CS32_SHIFT)
#define HF_SS32_MASK (1 << HF_SS32_SHIFT)

12
qemu/target-i386/translate.c
View file

@ -8986,9 +8986,9 @@ void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
dc->popl_esp_hack = 0;
/* select memory access functions */
dc->mem_index = 0;
if (flags & HF_SOFTMMU_MASK) {
dc->mem_index = cpu_mmu_index(env, false);
}
#ifdef CONFIG_SOFTMMU
dc->mem_index = cpu_mmu_index(env, false);
#endif
dc->cpuid_features = env->features[FEAT_1_EDX];
dc->cpuid_ext_features = env->features[FEAT_1_ECX];
dc->cpuid_ext2_features = env->features[FEAT_8000_0001_EDX];
@ -9001,11 +9001,7 @@ void gen_intermediate_code(CPUX86State *env, TranslationBlock *tb)
#endif
dc->flags = flags;
dc->jmp_opt = !(dc->tf || cs->singlestep_enabled ||
(flags & HF_INHIBIT_IRQ_MASK)
#ifndef CONFIG_SOFTMMU
|| (flags & HF_SOFTMMU_MASK)
#endif
);
(flags & HF_INHIBIT_IRQ_MASK));
/* Do not optimize repz jumps at all in icount mode, because
rep movsS instructions are execured with different paths
in !repz_opt and repz_opt modes. The first one was used