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cputlb: drop flush_global flag from tlb_flush

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We have never has the concept of global TLB entries which would avoid
the flush so we never actually use this flag. Drop it and make clear
that tlb_flush is the sledge-hammer it has always been.

Backports commit  d10eb08f5d8389c814b554d01aa2882ac58221bf from qemu
This commit is contained in:
Alex Bennée 2018-03-01 19:35:21 -05:00 committed by Lioncash
parent 7e2cc86ad2
commit e3e57ca08e
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
12 changed files with 47 additions and 59 deletions
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21
qemu/cputlb.c
View file

@ -69,24 +69,15 @@ static void tlb_set_dirty1(CPUTLBEntry *tlb_entry, target_ulong vaddr);
/* statistics */
//int tlb_flush_count;
/* NOTE:
* If flush_global is true (the usual case), flush all tlb entries.
* If flush_global is false, flush (at least) all tlb entries not
* marked global.
*
* Since QEMU doesn't currently implement a global/not-global flag
* for tlb entries, at the moment tlb_flush() will also flush all
* tlb entries in the flush_global == false case. This is OK because
* CPU architectures generally permit an implementation to drop
* entries from the TLB at any time, so flushing more entries than
* required is only an efficiency issue, not a correctness issue.
/* This is OK because CPU architectures generally permit an
* implementation to drop entries from the TLB at any time, so
* flushing more entries than required is only an efficiency issue,
* not a correctness issue.
*/
void tlb_flush(CPUState *cpu, int flush_global)
void tlb_flush(CPUState *cpu)
{
CPUArchState *env = cpu->env_ptr;
tlb_debug("(%d)\n", flush_global);
memset(env->tlb_table, -1, sizeof(env->tlb_table));
memset(env->tlb_v_table, -1, sizeof(env->tlb_v_table));
memset(cpu->tb_jmp_cache, 0, sizeof(cpu->tb_jmp_cache));
@ -111,7 +102,7 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr)
TARGET_FMT_lx "/" TARGET_FMT_lx ")\n",
env->tlb_flush_addr, env->tlb_flush_mask);
tlb_flush(cpu, 1);
tlb_flush(cpu);
return;
}

2
qemu/exec.c
View file

@ -1833,7 +1833,7 @@ static void tcg_commit(MemoryListener *listener)
d = atomic_read(&cpuas->as->dispatch);
// Unicorn: atomic_set used instead of atomic_rcu_set
atomic_set(&cpuas->memory_dispatch, d);
tlb_flush(cpuas->cpu, 1);
tlb_flush(cpuas->cpu);
}
void address_space_init_dispatch(AddressSpace *as)

15
qemu/include/exec/exec-all.h
View file

@ -107,16 +107,13 @@ void tlb_flush_page(CPUState *cpu, target_ulong addr);
/**
* tlb_flush:
* @cpu: CPU whose TLB should be flushed
* @flush_global: ignored
*
* Flush the entire TLB for the specified CPU.
* The flush_global flag is in theory an indicator of whether the whole
* TLB should be flushed, or only those entries not marked global.
* In practice QEMU does not implement any global/not global flag for
* TLB entries, and the argument is ignored.
* Flush the entire TLB for the specified CPU. Most CPU architectures
* allow the implementation to drop entries from the TLB at any time
* so this is generally safe. If more selective flushing is required
* use one of the other functions for efficiency.
*/
void tlb_flush(CPUState *cpu, int flush_global);
void tlb_flush(CPUState *cpu);
/**
* tlb_flush_page_by_mmuidx:
* @cpu: CPU whose TLB should be flushed
@ -180,7 +177,7 @@ static inline void tlb_flush_page(CPUState *cpu, target_ulong addr)
{
}
static inline void tlb_flush(CPUState *cpu, int flush_global)
static inline void tlb_flush(CPUState *cpu)
{
}

4
qemu/memory.c
View file

@ -50,7 +50,7 @@ MemoryRegion *memory_map(struct uc_struct *uc, hwaddr begin, size_t size, uint32
memory_region_add_subregion(get_system_memory(uc), begin, ram);
if (uc->current_cpu)
tlb_flush(uc->current_cpu, 1);
tlb_flush(uc->current_cpu);
return ram;
}
@ -69,7 +69,7 @@ MemoryRegion *memory_map_ptr(struct uc_struct *uc, hwaddr begin, size_t size, ui
memory_region_add_subregion(get_system_memory(uc), begin, ram);
if (uc->current_cpu)
tlb_flush(uc->current_cpu, 1);
tlb_flush(uc->current_cpu);
return ram;
}

2
qemu/qom/cpu.c
View file

@ -181,7 +181,7 @@ static void cpu_common_reset(CPUState *cpu)
}
#ifdef CONFIG_SOFTMMU
tlb_flush(cpu, 0);
tlb_flush(cpu);
#endif
//}
}

30
qemu/target-arm/helper.c
View file

@ -370,7 +370,7 @@ static void dacr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
ARMCPU *cpu = arm_env_get_cpu(env);
raw_write(env, ri, value);
tlb_flush(CPU(cpu), 1); /* Flush TLB as domain not tracked in TLB */
tlb_flush(CPU(cpu)); /* Flush TLB as domain not tracked in TLB */
}
static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
@ -381,7 +381,7 @@ static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
/* Unlike real hardware the qemu TLB uses virtual addresses,
* not modified virtual addresses, so this causes a TLB flush.
*/
tlb_flush(CPU(cpu), 1);
tlb_flush(CPU(cpu));
raw_write(env, ri, value);
}
}
@ -397,7 +397,7 @@ static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri,
* format) this register includes the ASID, so do a TLB flush.
* For PMSA it is purely a process ID and no action is needed.
*/
tlb_flush(CPU(cpu), 1);
tlb_flush(CPU(cpu));
}
raw_write(env, ri, value);
}
@ -408,7 +408,7 @@ static void tlbiall_write(CPUARMState *env, const ARMCPRegInfo *ri,
/* Invalidate all (TLBIALL) */
ARMCPU *cpu = arm_env_get_cpu(env);
tlb_flush(CPU(cpu), 1);
tlb_flush(CPU(cpu));
}
static void tlbimva_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -426,7 +426,7 @@ static void tlbiasid_write(CPUARMState *env, const ARMCPRegInfo *ri,
/* Invalidate by ASID (TLBIASID) */
ARMCPU *cpu = arm_env_get_cpu(env);
tlb_flush(CPU(cpu), value == 0);
tlb_flush(CPU(cpu));
}
static void tlbimvaa_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -444,7 +444,7 @@ static void tlbiall_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
{
//struct uc_struct *uc = env->uc;
// TODO: issue #642
// tlb_flush(other_cpu, 1);
// tlb_flush(other_cpu);
}
static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -452,7 +452,7 @@ static void tlbiasid_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
{
//struct uc_struct *uc = env->uc;
// TODO: issue #642
// tlb_flush(other_cpu, value == 0);
// tlb_flush(other_cpu);
}
static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -460,7 +460,7 @@ static void tlbimva_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
{
//struct uc_struct *uc = env->uc;
// TODO: issue #642
// tlb_flush(other_cpu, value & TARGET_PAGE_MASK);
// tlb_flush(other_cpu);
}
static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -468,7 +468,7 @@ static void tlbimvaa_is_write(CPUARMState *env, const ARMCPRegInfo *ri,
{
//struct uc_struct *uc = env->uc;
// TODO: issue #642
// tlb_flush(other_cpu, value & TARGET_PAGE_MASK);
// tlb_flush(other_cpu);
}
static void tlbiall_nsnh_write(CPUARMState *env, const ARMCPRegInfo *ri,
@ -2058,7 +2058,7 @@ static void pmsav7_write(CPUARMState *env, const ARMCPRegInfo *ri,
}
u32p += env->cp15.c6_rgnr;
tlb_flush(CPU(cpu), 1); /* Mappings may have changed - purge! */
tlb_flush(CPU(cpu)); /* Mappings may have changed - purge! */
*u32p = value;
}
@ -2183,7 +2183,7 @@ static void vmsa_ttbcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
/* With LPAE the TTBCR could result in a change of ASID
* via the TTBCR.A1 bit, so do a TLB flush.
*/
tlb_flush(CPU(cpu), 1);
tlb_flush(CPU(cpu));
}
vmsa_ttbcr_raw_write(env, ri, value);
}
@ -2207,7 +2207,7 @@ static void vmsa_tcr_el1_write(CPUARMState *env, const ARMCPRegInfo *ri,
TCR *tcr = raw_ptr(env, ri);
/* For AArch64 the A1 bit could result in a change of ASID, so TLB flush. */
tlb_flush(CPU(cpu), 1);
tlb_flush(CPU(cpu));
tcr->raw_tcr = value;
}
@ -2220,7 +2220,7 @@ static void vmsa_ttbr_write(CPUARMState *env, const ARMCPRegInfo *ri,
if (cpreg_field_is_64bit(ri)) {
ARMCPU *cpu = arm_env_get_cpu(env);
tlb_flush(CPU(cpu), 1);
tlb_flush(CPU(cpu));
}
raw_write(env, ri, value);
}
@ -2864,7 +2864,7 @@ static void sctlr_write(CPUARMState *env, const ARMCPRegInfo *ri,
raw_write(env, ri, value);
/* ??? Lots of these bits are not implemented. */
/* This may enable/disable the MMU, so do a TLB flush. */
tlb_flush(CPU(cpu), 1);
tlb_flush(CPU(cpu));
}
static CPAccessResult fpexc32_access(CPUARMState *env, const ARMCPRegInfo *ri,
@ -3223,7 +3223,7 @@ static void hcr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value)
* HCR_DC Disables stage1 and enables stage2 translation
*/
if ((raw_read(env, ri) ^ value) & (HCR_VM | HCR_PTW | HCR_DC)) {
tlb_flush(CPU(cpu), 1);
tlb_flush(CPU(cpu));
}
raw_write(env, ri, value);
}

2
qemu/target-i386/fpu_helper.c
View file

@ -1499,7 +1499,7 @@ void helper_xrstor(CPUX86State *env, target_ulong ptr, uint64_t rfbm)
}
if (env->pkru != old_pkru) {
CPUState *cs = CPU(x86_env_get_cpu(env));
tlb_flush(cs, 1);
tlb_flush(cs);
}
}
}

8
qemu/target-i386/helper.c
View file

@ -396,7 +396,7 @@ void x86_cpu_set_a20(X86CPU *cpu, int a20_state)
/* when a20 is changed, all the MMU mappings are invalid, so
we must flush everything */
tlb_flush(cs, 1);
tlb_flush(cs);
env->a20_mask = ~(1 << 20) | (a20_state << 20);
}
}
@ -411,7 +411,7 @@ void cpu_x86_update_cr0(CPUX86State *env, uint32_t new_cr0)
#endif
if ((new_cr0 & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK)) !=
(env->cr[0] & (CR0_PG_MASK | CR0_WP_MASK | CR0_PE_MASK))) {
tlb_flush(CPU(cpu), 1);
tlb_flush(CPU(cpu));
}
#ifdef TARGET_X86_64
@ -454,7 +454,7 @@ void cpu_x86_update_cr3(CPUX86State *env, target_ulong new_cr3)
#if defined(DEBUG_MMU)
printf("CR3 update: CR3=" TARGET_FMT_lx "\n", new_cr3);
#endif
tlb_flush(CPU(cpu), 0);
tlb_flush(CPU(cpu));
}
}
@ -469,7 +469,7 @@ void cpu_x86_update_cr4(CPUX86State *env, uint32_t new_cr4)
if ((new_cr4 ^ env->cr[4]) &
(CR4_PGE_MASK | CR4_PAE_MASK | CR4_PSE_MASK |
CR4_SMEP_MASK | CR4_SMAP_MASK | CR4_LA57_MASK)) {
tlb_flush(CPU(cpu), 1);
tlb_flush(CPU(cpu));
}
/* Clear bits we're going to recompute. */

2
qemu/target-i386/misc_helper.c
View file

@ -631,5 +631,5 @@ void helper_wrpkru(CPUX86State *env, uint32_t ecx, uint64_t val)
}
env->pkru = val;
tlb_flush(cs, 1);
tlb_flush(cs);
}

2
qemu/target-i386/svm_helper.c
View file

@ -286,7 +286,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int next_eip_addend)
break;
case TLB_CONTROL_FLUSH_ALL_ASID:
/* FIXME: this is not 100% correct but should work for now */
tlb_flush(cs, 1);
tlb_flush(cs);
break;
}

6
qemu/target-mips/op_helper.c
View file

@ -1410,7 +1410,7 @@ void helper_mtc0_entryhi(CPUMIPSState *env, target_ulong arg1)
/* If the ASID changes, flush qemu's TLB. */
if ((old & env->CP0_EntryHi_ASID_mask) !=
(val & env->CP0_EntryHi_ASID_mask)) {
cpu_mips_tlb_flush(env, 1);
cpu_mips_tlb_flush(env);
}
}
@ -1988,7 +1988,7 @@ void r4k_helper_tlbinv(CPUMIPSState *env)
tlb->EHINV = 1;
}
}
cpu_mips_tlb_flush(env, 1);
cpu_mips_tlb_flush(env);
}
void r4k_helper_tlbinvf(CPUMIPSState *env)
@ -1998,7 +1998,7 @@ void r4k_helper_tlbinvf(CPUMIPSState *env)
for (idx = 0; idx < env->tlb->nb_tlb; idx++) {
env->tlb->mmu.r4k.tlb[idx].EHINV = 1;
}
cpu_mips_tlb_flush(env, 1);
cpu_mips_tlb_flush(env);
}
void r4k_helper_tlbwi(CPUMIPSState *env)

12
qemu/target-sparc/ldst_helper.c
View file

@ -776,7 +776,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
case 2: /* flush region (16M) */
case 3: /* flush context (4G) */
case 4: /* flush entire */
tlb_flush(CPU(cpu), 1);
tlb_flush(CPU(cpu));
break;
default:
break;
@ -801,7 +801,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
are invalid in normal mode. */
if ((oldreg ^ env->mmuregs[reg])
& (MMU_NF | env->def->mmu_bm)) {
tlb_flush(CPU(cpu), 1);
tlb_flush(CPU(cpu));
}
break;
case 1: /* Context Table Pointer Register */
@ -812,7 +812,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val,
if (oldreg != env->mmuregs[reg]) {
/* we flush when the MMU context changes because
QEMU has no MMU context support */
tlb_flush(CPU(cpu), 1);
tlb_flush(CPU(cpu));
}
break;
case 3: /* Synchronous Fault Status Register with Clear */
@ -1520,13 +1520,13 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val,
env->dmmu.mmu_primary_context = val;
/* can be optimized to only flush MMU_USER_IDX
and MMU_KERNEL_IDX entries */
tlb_flush(CPU(cpu), 1);
tlb_flush(CPU(cpu));
break;
case 2: /* Secondary context */
env->dmmu.mmu_secondary_context = val;
/* can be optimized to only flush MMU_USER_SECONDARY_IDX
and MMU_KERNEL_SECONDARY_IDX entries */
tlb_flush(CPU(cpu), 1);
tlb_flush(CPU(cpu));
break;
case 5: /* TSB access */
DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"
@ -1665,7 +1665,7 @@ void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr,
/* flush neverland mappings created during no-fault mode,
so the sequential MMU faults report proper fault types */
if (env->mmuregs[0] & MMU_NF) {
tlb_flush(cs, 1);
tlb_flush(cs);
}
}
#else