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cpu: Define CPUArchState with typedef

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For all targets, do this just before including exec/cpu-all.h.

Backports commit 4f7c64b3819d559417615ed2b1d028ebc1a49580 from qemu
This commit is contained in:
Richard Henderson 2019-06-12 11:06:27 -04:00 committed by Lioncash
parent 5e5197b136
commit e3f1f25996
No known key found for this signature in database
GPG key ID: 4E3C3CC1031BA9C7
6 changed files with 12 additions and 14 deletions
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4
qemu/target/arm/cpu.h
View file

@ -31,8 +31,6 @@
/* ARM processors have a weak memory model */
#define TCG_GUEST_DEFAULT_MO (0)
#define CPUArchState struct CPUARMState
#define EXCP_UDEF 1 /* undefined instruction */
#define EXCP_SWI 2 /* software interrupt */
#define EXCP_PREFETCH_ABORT 3
@ -3081,6 +3079,8 @@ static inline bool arm_cpu_data_is_big_endian(CPUARMState *env)
}
}
typedef CPUARMState CPUArchState;
#include "exec/cpu-all.h"
/* Bit usage in the TB flags field: bit 31 indicates whether we are

4
qemu/target/i386/cpu.h
View file

@ -42,8 +42,6 @@
#define ELF_MACHINE_UNAME "i686"
#endif
#define CPUArchState struct CPUX86State
#include "exec/cpu-defs.h"
#define R_EAX 0
@ -1672,6 +1670,8 @@ static inline target_long lshift(target_long x, int n)
/* translate.c */
void tcg_x86_init(struct uc_struct *);
typedef CPUX86State CPUArchState;
#include "exec/cpu-all.h"
#include "svm.h"

4
qemu/target/m68k/cpu.h
View file

@ -26,8 +26,6 @@
#include "cpu-qom.h"
#include "exec/cpu-defs.h"
#define CPUArchState struct CPUM68KState
#define OS_BYTE 0
#define OS_WORD 1
#define OS_LONG 2
@ -533,6 +531,8 @@ void m68k_cpu_transaction_failed(CPUState *cs, hwaddr physaddr, vaddr addr,
int mmu_idx, MemTxAttrs attrs,
MemTxResult response, uintptr_t retaddr);
typedef CPUM68KState CPUArchState;
#include "exec/cpu-all.h"
/* TB flags */

6
qemu/target/mips/cpu.h
View file

@ -3,8 +3,6 @@
#define ALIGNED_ONLY
#define CPUArchState struct CPUMIPSState
#include "config.h"
#include "qemu-common.h"
#include "cpu-qom.h"
@ -12,8 +10,6 @@
#include "fpu/softfloat.h"
#include "mips-defs.h"
struct CPUMIPSState;
typedef struct CPUMIPSTLBContext CPUMIPSTLBContext;
/* MSA Context */
@ -1116,6 +1112,8 @@ static inline int cpu_mmu_index(CPUMIPSState *env, bool ifetch)
return hflags_mmu_index(env->hflags);
}
typedef CPUMIPSState CPUArchState;
#include "exec/cpu-all.h"
/*

4
qemu/target/riscv/cpu.h
View file

@ -92,8 +92,6 @@ enum {
#define MAX_RISCV_PMPS (16)
typedef struct CPURISCVState CPURISCVState;
#include "pmp.h"
struct CPURISCVState {
@ -331,6 +329,8 @@ typedef struct {
void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops);
void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops);
typedef CPURISCVState CPUArchState;
#include "exec/cpu-all.h"
// Unicorn-specific

4
qemu/target/sparc/cpu.h
View file

@ -14,8 +14,6 @@
#define TARGET_DPREGS 32
#endif
#define CPUArchState struct CPUSPARCState
/*#define EXCP_INTERRUPT 0x100*/
/* trap definitions */
@ -720,6 +718,8 @@ static inline int cpu_pil_allowed(CPUSPARCState *env1, int pil)
#endif
}
typedef CPUSPARCState CPUArchState;
#include "exec/cpu-all.h"
#ifdef TARGET_SPARC64