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target/arm: Simplify disas_thumb2_insn

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Fold away all of the cases that now just goto illegal_op,
because all of their internal bits are now in decodetree.

Backports commit f843e77144c9334e244a422848177f2fbef5eb05 from qemu
This commit is contained in:
Richard Henderson 2019-11-20 11:57:43 -05:00 committed by Lioncash
parent 1b5c72935d
commit e402eef2f0
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GPG key ID: 4E3C3CC1031BA9C7
1 changed files with 4 additions and 77 deletions
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81
qemu/target/arm/translate.c
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@ -10905,10 +10905,6 @@ static bool thumb_insn_is_16bit(DisasContext *s, uint32_t pc, uint32_t insn)
/* Translate a 32-bit thumb instruction. */
static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
{
TCGContext *tcg_ctx = s->uc->tcg_ctx;
uint32_t rn;
int op;
/*
* ARMv6-M supports a limited subset of Thumb2 instructions.
* Other Thumb1 architectures allow only 32-bit
@ -10949,35 +10945,10 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
/* fall back to legacy decoder */
rn = (insn >> 16) & 0xf;
switch ((insn >> 25) & 0xf) {
case 0: case 1: case 2: case 3:
/* 16-bit instructions. Should never happen. */
abort();
case 4:
/* All in decodetree */
goto illegal_op;
case 5:
/* All in decodetree */
goto illegal_op;
case 13: /* Misc data processing. */
op = ((insn >> 22) & 6) | ((insn >> 7) & 1);
if (op < 4 && (insn & 0xf000) != 0xf000)
goto illegal_op;
switch (op) {
case 0: /* Register controlled shift, in decodetree */
goto illegal_op;
case 1: /* Sign/zero extend, in decodetree */
case 2: /* SIMD add/subtract, in decodetree */
case 3: /* Other data processing, in decodetree */
goto illegal_op;
case 4: case 5:
/* 32-bit multiply. Sum of absolute differences, in decodetree */
goto illegal_op;
case 6: case 7: /* 64-bit multiply, Divide, in decodetree */
goto illegal_op;
}
break;
case 6: case 7: case 14: case 15:
/* Coprocessor. */
if (arm_dc_feature(s, ARM_FEATURE_M)) {
@ -11006,6 +10977,8 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
if (arm_dc_feature(s, ARM_FEATURE_VFP)) {
TCGContext *tcg_ctx = s->uc->tcg_ctx;
uint32_t rn = (insn >> 16) & 0xf;
TCGv_i32 fptr = load_reg(s, rn);
if (extract32(insn, 20, 1)) {
@ -11064,50 +11037,6 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
}
break;
case 8: case 9: case 10: case 11:
if (insn & (1 << 15)) {
/* Branches, misc control. */
if (insn & 0x5000) {
/* Unconditional branch, in decodetree */
goto illegal_op;
} else if (((insn >> 23) & 7) == 7) {
/* Misc control */
if (insn & (1 << 13))
goto illegal_op;
if (insn & (1 << 26)) {
/* hvc, smc, in decodetree */
goto illegal_op;
} else {
op = (insn >> 20) & 7;
switch (op) {
case 0: /* msr cpsr, in decodetree */
case 1: /* msr spsr, in decodetree */
goto illegal_op;
case 2: /* cps, nop-hint, in decodetree */
goto illegal_op;
case 3: /* Special control operations, in decodetree */
case 4: /* bxj, in decodetree */
goto illegal_op;
case 5: /* Exception return. */
case 6: /* MRS, in decodetree */
case 7: /* MSR, in decodetree */
goto illegal_op;
}
}
} else {
/* Conditional branch, in decodetree */
goto illegal_op;
}
} else {
/*
* 0b1111_0xxx_xxxx_0xxx_xxxx_xxxx
* - Data-processing (modified immediate, plain binary immediate)
* All in decodetree.
*/
goto illegal_op;
}
break;
case 12:
if ((insn & 0x01100000) == 0x01000000) {
if (disas_neon_ls_insn(s, insn)) {
@ -11115,14 +11044,12 @@ static void disas_thumb2_insn(DisasContext *s, uint32_t insn)
}
break;
}
/* Load/store single data item, in decodetree */
goto illegal_op;
default:
goto illegal_op;
illegal_op:
unallocated_encoding(s);
}
return;
illegal_op:
unallocated_encoding(s);
}
static void disas_thumb_insn(DisasContext *s, uint32_t insn)