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target/arm: Mask CPSR_J when Jazelle is not enabled

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The J bit signals Jazelle mode, and so of course is RES0
when the feature is not enabled.

Backports commit f062d1447f2a80e7a5f593b8cb5ac7cab5e16eb0 from qemu
This commit is contained in:
Richard Henderson 2020-03-21 17:17:48 -04:00 committed by Lioncash
parent ca2bb77ab3
commit e4a7a089f0
1 changed files with 4 additions and 1 deletions
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5
qemu/target/arm/internals.h
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@ -1066,7 +1066,7 @@ static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx)
static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features, static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features,
const ARMISARegisters *id) const ARMISARegisters *id)
{ {
uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV | CPSR_J; uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV;
if ((features >> ARM_FEATURE_V4T) & 1) { if ((features >> ARM_FEATURE_V4T) & 1) {
valid |= CPSR_T; valid |= CPSR_T;
@ -1080,6 +1080,9 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features,
if ((features >> ARM_FEATURE_THUMB2) & 1) { if ((features >> ARM_FEATURE_THUMB2) & 1) {
valid |= CPSR_IT; valid |= CPSR_IT;
} }
if (isar_feature_jazelle(id)) {
valid |= CPSR_J;
}
return valid; return valid;
} }