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target/arm: Mask CPSR_J when Jazelle is not enabled
The J bit signals Jazelle mode, and so of course is RES0 when the feature is not enabled. Backports commit f062d1447f2a80e7a5f593b8cb5ac7cab5e16eb0 from qemu
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@ -1066,7 +1066,7 @@ static inline bool arm_mmu_idx_is_stage1_of_2(ARMMMUIdx mmu_idx)
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static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features,
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static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features,
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const ARMISARegisters *id)
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const ARMISARegisters *id)
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{
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{
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uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV | CPSR_J;
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uint32_t valid = CPSR_M | CPSR_AIF | CPSR_IL | CPSR_NZCV;
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if ((features >> ARM_FEATURE_V4T) & 1) {
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if ((features >> ARM_FEATURE_V4T) & 1) {
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valid |= CPSR_T;
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valid |= CPSR_T;
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@ -1080,6 +1080,9 @@ static inline uint32_t aarch32_cpsr_valid_mask(uint64_t features,
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if ((features >> ARM_FEATURE_THUMB2) & 1) {
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if ((features >> ARM_FEATURE_THUMB2) & 1) {
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valid |= CPSR_IT;
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valid |= CPSR_IT;
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}
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}
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if (isar_feature_jazelle(id)) {
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valid |= CPSR_J;
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}
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return valid;
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return valid;
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}
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}
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