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target/i386: add fast short REP MOV support

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For CPUs support fast short REP MOV[CPUID.(EAX=7,ECX=0):EDX(bit4)], e.g
Icelake and Tigerlake, expose it to the guest VM.

Backports commit 5cb287d2bd578dfe4897458793b4fce35bc4f744 from qemu
This commit is contained in:
Chenyi Qiang 2021-02-25 23:31:33 -05:00 committed by Lioncash
parent 113dc25fbf
commit e5d9e0ed53
2 changed files with 3 additions and 1 deletions
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2
qemu/target/i386/cpu.c
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@ -875,7 +875,7 @@ static FeatureWordInfo feature_word_info[FEATURE_WORDS] = {
.type = CPUID_FEATURE_WORD, .type = CPUID_FEATURE_WORD,
.feat_names = { .feat_names = {
NULL, NULL, "avx512-4vnniw", "avx512-4fmaps", NULL, NULL, "avx512-4vnniw", "avx512-4fmaps",
NULL, NULL, NULL, NULL, "fsrm", NULL, NULL, NULL,
NULL, NULL, "md-clear", NULL, NULL, NULL, "md-clear", NULL,
NULL, NULL, NULL, NULL, NULL, NULL, NULL, NULL,
NULL, NULL, NULL /* pconfig */, NULL, NULL, NULL, NULL /* pconfig */, NULL,

2
qemu/target/i386/cpu.h
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@ -723,6 +723,8 @@ typedef uint64_t FeatureWordArray[FEATURE_WORDS];
#define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2) #define CPUID_7_0_EDX_AVX512_4VNNIW (1U << 2)
/* AVX512 Multiply Accumulation Single Precision */ /* AVX512 Multiply Accumulation Single Precision */
#define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3) #define CPUID_7_0_EDX_AVX512_4FMAPS (1U << 3)
/* Fast Short Rep Mov */
#define CPUID_7_0_EDX_FSRM (1U << 4)
/* Speculation Control */ /* Speculation Control */
#define CPUID_7_0_EDX_SPEC_CTRL (1U << 26) #define CPUID_7_0_EDX_SPEC_CTRL (1U << 26)
/* Single Thread Indirect Branch Predictors */ /* Single Thread Indirect Branch Predictors */