mirror of
https://github.com/yuzu-emu/unicorn.git
synced 2024-12-23 01:15:37 +00:00
i386: Register versioned CPU models
Add support for registration of multiple versions of CPU models. The existing CPU models will be registered with a "-v1" suffix. The -noTSX, -IBRS, and -IBPB CPU model variants will become versions of the original models in a separate patch, so make sure we register no versions for them. Backports commit dcafd1ef0af227ef87f7a6dec8fc66d7d2e2442d from qemu
This commit is contained in:
Eduardo Habkost
Lioncash
parent
1e48962847
commit
e5e5c2fd6c
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@ -36,13 +36,7 @@
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#define X86_CPU_GET_CLASS(uc, obj) \
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OBJECT_GET_CLASS(uc, X86CPUClass, (obj), TYPE_X86_CPU)
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/**
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* X86CPUDefinition:
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*
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* CPU model definition data that was not converted to QOM per-subclass
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* property defaults yet.
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*/
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typedef struct X86CPUDefinition X86CPUDefinition;
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typedef struct X86CPUModel X86CPUModel;
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/**
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* X86CPUClass:
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@ -59,7 +53,7 @@ typedef struct X86CPUClass {
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/*< public >*/
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/* Should be eventually replaced by subclass-specific property defaults. */
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X86CPUDefinition *cpu_def;
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X86CPUModel *model;
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bool kvm_required;
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@ -1537,7 +1537,17 @@ static ObjectClass *x86_cpu_class_by_name(struct uc_struct *uc, const char *cpu_
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return oc;
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}
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struct X86CPUDefinition {
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typedef struct PropValue {
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const char *prop, *value;
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} PropValue;
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typedef struct X86CPUVersionDefinition {
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X86CPUVersion version;
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PropValue *props;
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} X86CPUVersionDefinition;
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/* Base definition for a CPU model */
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typedef struct X86CPUDefinition {
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const char *name;
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uint32_t level;
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uint32_t xlevel;
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@ -1550,8 +1560,41 @@ struct X86CPUDefinition {
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const char *model_id;
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bool cache_info_passthrough;
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CPUCaches *cache_info;
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/*
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* Definitions for alternative versions of CPU model.
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* List is terminated by item with version == 0.
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* If NULL, version 1 will be registered automatically.
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*/
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const X86CPUVersionDefinition *versions;
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} X86CPUDefinition;
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/* Reference to a specific CPU model version */
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struct X86CPUModel {
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/* Base CPU definition */
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X86CPUDefinition *cpudef;
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/* CPU model version */
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X86CPUVersion version;
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};
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/* Get full model name for CPU version */
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static char *x86_cpu_versioned_model_name(X86CPUDefinition *cpudef,
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X86CPUVersion version)
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{
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assert(version > 0);
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return g_strdup_printf("%s-v%d", cpudef->name, (int)version);
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}
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static const X86CPUVersionDefinition *x86_cpu_def_get_versions(X86CPUDefinition *def)
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{
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/* When X86CPUDefinition::versions is NULL, we register only v1 */
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static const X86CPUVersionDefinition default_version_list[] = {
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{ 1 },
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{ /* end of list */ }
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};
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return def->versions ?: default_version_list;
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}
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static CPUCacheInfo epyc_l1d_cache = {
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.type = DATA_CACHE,
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.level = 1,
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@ -1946,6 +1989,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_EXT3_LAHF_LM,
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.xlevel = 0x80000008,
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.model_id = "Intel Core i7 9xx (Nehalem Core i7, IBRS update)",
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/*
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* This CPU model will eventually be replaced by an alias,
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* don't register any versions for it.
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*/
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.versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
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},
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{
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.name = "Westmere",
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@ -2000,6 +2048,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_6_EAX_ARAT,
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.xlevel = 0x80000008,
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.model_id = "Westmere E56xx/L56xx/X56xx (IBRS update)",
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/*
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* This CPU model will eventually be replaced by an alias,
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* don't register any versions for it.
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*/
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.versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
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},
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{
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.name = "SandyBridge",
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@ -2064,6 +2117,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_6_EAX_ARAT,
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.xlevel = 0x80000008,
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.model_id = "Intel Xeon E312xx (Sandy Bridge, IBRS update)",
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/*
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* This CPU model will eventually be replaced by an alias,
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* don't register any versions for it.
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*/
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.versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
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},
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{
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.name = "IvyBridge",
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@ -2134,6 +2192,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_6_EAX_ARAT,
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.xlevel = 0x80000008,
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.model_id = "Intel Xeon E3-12xx v2 (Ivy Bridge, IBRS)",
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/*
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* This CPU model will eventually be replaced by an alias,
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* don't register any versions for it.
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*/
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.versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
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},
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{
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.name = "Haswell-noTSX",
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@ -2170,6 +2233,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_6_EAX_ARAT,
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.xlevel = 0x80000008,
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.model_id = "Intel Core Processor (Haswell, no TSX)",
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/*
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* This CPU model will eventually be replaced by an alias,
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* don't register any versions for it.
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*/
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.versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
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},
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{
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.name = "Haswell-noTSX-IBRS",
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@ -2208,6 +2276,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_6_EAX_ARAT,
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.xlevel = 0x80000008,
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.model_id = "Intel Core Processor (Haswell, no TSX, IBRS)",
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/*
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* This CPU model will eventually be replaced by an alias,
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* don't register any versions for it.
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*/
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.versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
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},
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{
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.name = "Haswell",
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@ -2284,6 +2357,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_6_EAX_ARAT,
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.xlevel = 0x80000008,
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.model_id = "Intel Core Processor (Haswell, IBRS)",
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/*
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* This CPU model will eventually be replaced by an alias,
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* don't register any versions for it.
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*/
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.versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
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},
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{
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.name = "Broadwell-noTSX",
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@ -2322,6 +2400,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_6_EAX_ARAT,
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.xlevel = 0x80000008,
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.model_id = "Intel Core Processor (Broadwell, no TSX)",
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/*
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* This CPU model will eventually be replaced by an alias,
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* don't register any versions for it.
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*/
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.versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
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},
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{
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.name = "Broadwell-noTSX-IBRS",
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@ -2362,6 +2445,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_6_EAX_ARAT,
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.xlevel = 0x80000008,
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.model_id = "Intel Core Processor (Broadwell, no TSX, IBRS)",
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/*
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* This CPU model will eventually be replaced by an alias,
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* don't register any versions for it.
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*/
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.versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
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},
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{
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.name = "Broadwell",
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@ -2440,6 +2528,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_6_EAX_ARAT,
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.xlevel = 0x80000008,
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.model_id = "Intel Core Processor (Broadwell, IBRS)",
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/*
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* This CPU model will eventually be replaced by an alias,
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* don't register any versions for it.
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*/
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.versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
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},
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{
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.name = "Skylake-Client",
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@ -2532,6 +2625,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_6_EAX_ARAT,
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.xlevel = 0x80000008,
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.model_id = "Intel Core Processor (Skylake, IBRS)",
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/*
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* This CPU model will eventually be replaced by an alias,
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* don't register any versions for it.
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*/
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.versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
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},
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{
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.name = "Skylake-Server",
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@ -2634,6 +2732,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
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CPUID_6_EAX_ARAT,
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.xlevel = 0x80000008,
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.model_id = "Intel Xeon Processor (Skylake, IBRS)",
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/*
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* This CPU model will eventually be replaced by an alias,
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* don't register any versions for it.
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*/
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.versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
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},
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{
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.name = "Cascadelake-Server",
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@ -3142,6 +3245,11 @@ static X86CPUDefinition builtin_x86_defs[] = {
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.xlevel = 0x8000001E,
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.model_id = "AMD EPYC Processor (with IBPB)",
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.cache_info = &epyc_cache_info,
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/*
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* This CPU model will eventually be replaced by an alias,
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* don't register any versions for it.
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*/
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.versions = (X86CPUVersionDefinition[]) { { /* end of list */ } },
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},
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{
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.name = "Dhyana",
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@ -3195,10 +3303,6 @@ static X86CPUDefinition builtin_x86_defs[] = {
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},
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};
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typedef struct PropValue {
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const char *prop, *value;
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} PropValue;
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/* TCG-specific defaults that override all CPU models when using TCG
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*/
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static PropValue tcg_default_props[] = {
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@ -3745,10 +3849,62 @@ static void x86_cpu_apply_props(X86CPU *cpu, PropValue *props)
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}
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}
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static X86CPUVersion x86_cpu_model_last_version(const X86CPUModel *model)
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{
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int v = 0;
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const X86CPUVersionDefinition *vdef =
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x86_cpu_def_get_versions(model->cpudef);
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while (vdef->version) {
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v = vdef->version;
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vdef++;
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}
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return v;
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}
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/* Return the actual version being used for a specific CPU model */
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static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model)
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{
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X86CPUVersion v = model->version;
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if (v == CPU_VERSION_LATEST) {
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return x86_cpu_model_last_version(model);
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}
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return v;
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}
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/* Apply properties for the CPU model version specified in model */
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static void x86_cpu_apply_version_props(X86CPU *cpu, X86CPUModel *model)
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{
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const X86CPUVersionDefinition *vdef;
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X86CPUVersion version = x86_cpu_model_resolve_version(model);
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if (version == CPU_VERSION_LEGACY) {
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return;
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}
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for (vdef = x86_cpu_def_get_versions(model->cpudef); vdef->version; vdef++) {
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PropValue *p;
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for (p = vdef->props; p && p->prop; p++) {
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object_property_parse(cpu->env.uc, OBJECT(cpu), p->value, p->prop,
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&error_abort);
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}
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if (vdef->version == version) {
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break;
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}
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}
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/*
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* If we reached the end of the list, version number was invalid
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*/
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assert(vdef->version == version);
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}
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/* Load data from X86CPUDefinition
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*/
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static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
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static void x86_cpu_load_model(X86CPU *cpu, X86CPUModel *model, Error **errp)
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{
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X86CPUDefinition *def = model->cpudef;
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CPUX86State *env = &cpu->env;
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const char *vendor;
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FeatureWord w;
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@ -3784,43 +3940,65 @@ static void x86_cpu_load_def(X86CPU *cpu, X86CPUDefinition *def, Error **errp)
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vendor = def->vendor;
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object_property_set_str(env->uc, OBJECT(cpu), vendor, "vendor", errp);
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x86_cpu_apply_version_props(cpu, model);
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}
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static void x86_cpu_cpudef_class_init(struct uc_struct *uc, ObjectClass *oc, void *data)
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{
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X86CPUDefinition *cpudef = data;
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X86CPUModel *model = data;
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X86CPUClass *xcc = X86_CPU_CLASS(uc, oc);
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xcc->cpu_def = cpudef;
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xcc->model = model;
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}
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static void x86_register_cpudef_type(struct uc_struct *uc, X86CPUDefinition *def)
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static void x86_register_cpu_model_type(struct uc_struct *uc, const char *name, X86CPUModel *model)
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{
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char *typename = x86_cpu_type_name(def->name);
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char *typename = x86_cpu_type_name(name);
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TypeInfo ti = {
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typename,
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TYPE_X86_CPU,
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0,
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0,
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NULL,
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NULL,
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NULL,
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NULL,
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def,
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x86_cpu_cpudef_class_init,
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.name = typename,
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.parent = TYPE_X86_CPU,
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.class_init = x86_cpu_cpudef_class_init,
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.class_data = model,
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};
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/* catch mistakes instead of silently truncating model_id when too long */
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assert(def->model_id && strlen(def->model_id) <= 48);
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type_register(uc, &ti);
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g_free(typename);
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}
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static void x86_register_cpudef_types(struct uc_struct *uc, X86CPUDefinition *def)
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{
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X86CPUModel *m;
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const X86CPUVersionDefinition *vdef;
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char *name;
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/* AMD aliases are handled at runtime based on CPUID vendor, so
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* they shouldn't be set on the CPU model table.
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*/
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assert(!(def->features[FEAT_8000_0001_EDX] & CPUID_EXT2_AMD_ALIASES));
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/* catch mistakes instead of silently truncating model_id when too long */
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assert(def->model_id && strlen(def->model_id) <= 48);
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/* Unversioned model: */
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m = g_new0(X86CPUModel, 1);
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m->cpudef = def;
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m->version = CPU_VERSION_LEGACY;
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x86_register_cpu_model_type(uc, def->name, m);
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/* Versioned models: */
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for (vdef = x86_cpu_def_get_versions(def); vdef->version; vdef++) {
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X86CPUModel *m = g_new0(X86CPUModel, 1);
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m->cpudef = def;
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m->version = vdef->version;
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name = x86_cpu_versioned_model_name(def, vdef->version);
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x86_register_cpu_model_type(uc, name, m);
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g_free(name);
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}
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}
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#if !defined(CONFIG_USER_ONLY)
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void cpu_clear_apic_feature(CPUX86State *env)
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@ -4580,7 +4758,7 @@ static void x86_cpu_enable_xsave_components(X86CPU *cpu)
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* involved in setting up CPUID data are:
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*
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* 1) Loading CPU model definition (X86CPUDefinition). This is
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* implemented by x86_cpu_load_def() and should be completely
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* implemented by x86_cpu_load_model() and should be completely
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* transparent, as it is done automatically by instance_init.
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* No code should need to look at X86CPUDefinition structs
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* outside instance_init.
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@ -4805,7 +4983,7 @@ static int x86_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
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/* Cache information initialization */
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if (!cpu->legacy_cache) {
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/* Unicorn: commented out
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if (!xcc->cpu_def || !xcc->cpu_def->cache_info) {
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if (!xcc->model || !xcc->model->cpudef->cache_info) {
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char *name = x86_cpu_class_get_model_name(xcc);
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error_setg(errp,
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"CPU model '%s' doesn't support legacy-cache=off", name);
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@ -4814,7 +4992,7 @@ static int x86_cpu_realizefn(struct uc_struct *uc, DeviceState *dev, Error **err
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}
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*/
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env->cache_info_cpuid2 = env->cache_info_cpuid4 = env->cache_info_amd =
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*xcc->cpu_def->cache_info;
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*xcc->model->cpudef->cache_info;
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} else {
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/* Build legacy cache information */
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env->cache_info_cpuid2.l1d_cache = &legacy_l1d_cache;
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@ -4966,7 +5144,7 @@ static void x86_cpu_initfn(struct uc_struct *uc, Object *obj, void *opaque)
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// from qemu, but left this in to keep the member value initialized
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cpu->apic_id = UNASSIGNED_APIC_ID;
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x86_cpu_load_def(cpu, xcc->cpu_def, &error_abort);
|
||||
x86_cpu_load_model(cpu, xcc->model, &error_abort);
|
||||
}
|
||||
|
||||
static int64_t x86_cpu_get_arch_id(CPUState *cs)
|
||||
|
|
@ -5115,6 +5293,6 @@ void x86_cpu_register_types(void *opaque)
|
|||
|
||||
type_register(opaque, &x86_cpu_type_info);
|
||||
for (i = 0; i < ARRAY_SIZE(builtin_x86_defs); i++) {
|
||||
x86_register_cpudef_type(opaque, &builtin_x86_defs[i]);
|
||||
x86_register_cpudef_types(opaque, &builtin_x86_defs[i]);
|
||||
}
|
||||
}
|
||||
|
|
|
|||
|
|
@ -1801,6 +1801,16 @@ void cpu_report_tpr_access(CPUX86State *env, TPRAccess access);
|
|||
void x86_cpu_compat_kvm_no_autoenable(FeatureWord w, uint32_t features);
|
||||
void x86_cpu_compat_kvm_no_autodisable(FeatureWord w, uint32_t features);
|
||||
|
||||
/* Special values for X86CPUVersion: */
|
||||
|
||||
/* Resolve to latest CPU version */
|
||||
#define CPU_VERSION_LATEST -1
|
||||
|
||||
/* Don't resolve to any versioned CPU models, like old QEMU versions */
|
||||
#define CPU_VERSION_LEGACY 0
|
||||
|
||||
typedef int X86CPUVersion;
|
||||
|
||||
/* Return name of 32-bit register, from a R_* constant */
|
||||
const char *get_register_name_32(unsigned int reg);
|
||||
|
||||
|
|
|
|||
Loading…
Reference in a new issue