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target/arm: Add PAuth active bit to tbflags
There are 5 bits of state that could be added, but to save space within tbflags, add only a single enable bit. Helpers will determine the rest of the state at runtime. Backports commit 0816ef1bfcd3ac53e7454b62ca436727887f6056 from qemu
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@ -2962,6 +2962,7 @@ FIELD(TBFLAG_A64, TBI0, 0, 1)
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FIELD(TBFLAG_A64, TBI1, 1, 1)
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FIELD(TBFLAG_A64, SVEEXC_EL, 2, 2)
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FIELD(TBFLAG_A64, ZCR_LEN, 4, 4)
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FIELD(TBFLAG_A64, PAUTH_ACTIVE, 8, 1)
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static inline bool bswap_code(bool sctlr_b)
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{
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@ -12187,6 +12187,25 @@ void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc,
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flags = FIELD_DP32(flags, TBFLAG_A64, SVEEXC_EL, sve_el);
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flags = FIELD_DP32(flags, TBFLAG_A64, ZCR_LEN, zcr_len);
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}
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if (cpu_isar_feature(aa64_pauth, cpu)) {
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/*
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* In order to save space in flags, we record only whether
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* pauth is "inactive", meaning all insns are implemented as
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* a nop, or "active" when some action must be performed.
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* The decision of which action to take is left to a helper.
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*/
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uint64_t sctlr;
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if (current_el == 0) {
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/* FIXME: ARMv8.1-VHE S2 translation regime. */
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sctlr = env->cp15.sctlr_el[1];
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} else {
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sctlr = env->cp15.sctlr_el[current_el];
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}
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if (sctlr & (SCTLR_EnIA | SCTLR_EnIB | SCTLR_EnDA | SCTLR_EnDB)) {
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flags = FIELD_DP32(flags, TBFLAG_A64, PAUTH_ACTIVE, 1);
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}
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}
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} else {
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*pc = env->regs[15];
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flags = FIELD_DP32(flags, TBFLAG_A32, THUMB, env->thumb);
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@ -13599,6 +13599,7 @@ static void aarch64_tr_init_disas_context(DisasContextBase *dcbase,
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dc->fp_excp_el = FIELD_EX32(tb_flags, TBFLAG_ANY, FPEXC_EL);
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dc->sve_excp_el = FIELD_EX32(tb_flags, TBFLAG_A64, SVEEXC_EL);
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dc->sve_len = (FIELD_EX32(tb_flags, TBFLAG_A64, ZCR_LEN) + 1) * 16;
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dc->pauth_active = FIELD_EX32(tb_flags, TBFLAG_A64, PAUTH_ACTIVE);
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dc->vec_len = 0;
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dc->vec_stride = 0;
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dc->cp_regs = arm_cpu->cp_regs;
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@ -67,6 +67,8 @@ typedef struct DisasContext {
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bool is_ldex;
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/* True if a single-step exception will be taken to the current EL */
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bool ss_same_el;
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/* True if v8.3-PAuth is active. */
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bool pauth_active;
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/* Bottom two bits of XScale c15_cpar coprocessor access control reg */
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int c15_cpar;
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/* TCG op of the current insn_start. */
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