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target/arm: Correct handling of PMCR_EL0.LC bit
The LC bit in the PMCR_EL0 register is supposed to be: * read/write * RES1 on an AArch64-only implementation * an architecturally UNKNOWN value on reset (and use of LC==0 by software is deprecated). We were implementing it incorrectly as read-only always zero, though we do have all the code needed to test it and behave accordingly. Instead make it a read-write bit which resets to 1 always, which satisfies all the architectural requirements above. Backports commit 62d96ff48510f4bf648ad12f5d3a5507227b026f from qemu
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@ -877,6 +877,11 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
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#define PMCRC 0x4
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#define PMCRP 0x2
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#define PMCRE 0x1
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/*
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* Mask of PMCR bits writeable by guest (not including WO bits like C, P,
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* which can be written as 1 to trigger behaviour but which stay RAZ).
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*/
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#define PMCR_WRITEABLE_MASK (PMCRLC | PMCRDP | PMCRX | PMCRD | PMCRE)
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#define PMXEVTYPER_P 0x80000000
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#define PMXEVTYPER_U 0x40000000
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@ -1375,8 +1380,8 @@ static void pmcr_write(CPUARMState *env, const ARMCPRegInfo *ri,
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}
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/* only the DP, X, D and E bits are writable */
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env->cp15.c9_pmcr &= ~0x39;
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env->cp15.c9_pmcr |= (value & 0x39);
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env->cp15.c9_pmcr &= ~PMCR_WRITEABLE_MASK;
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env->cp15.c9_pmcr |= (value & PMCR_WRITEABLE_MASK);
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pmu_op_finish(env);
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}
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@ -6165,7 +6170,8 @@ static void define_pmu_regs(ARMCPU *cpu)
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.access = PL0_RW, .accessfn = pmreg_access,
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.type = ARM_CP_IO,
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.fieldoffset = offsetof(CPUARMState, cp15.c9_pmcr),
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.resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT),
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.resetvalue = (cpu->midr & 0xff000000) | (pmcrn << PMCRN_SHIFT) |
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PMCRLC,
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.writefn = pmcr_write, .raw_writefn = raw_write,
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};
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define_one_arm_cp_reg(cpu, &pmcr);
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