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target/riscv: Use background registers also for MSTATUS_MPV

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The current condition for the use of background registers only
considers the hypervisor load and store instructions,
but not accesses from M mode via MSTATUS_MPRV+MPV.

Backports db9ab38b81058b41e5f469165067feea46762eee
This commit is contained in:
Georg Kotheimer 2021-03-30 15:14:11 -04:00 committed by Lioncash
parent a392976e77
commit e74588a57f
1 changed files with 1 additions and 1 deletions
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2
qemu/target/riscv/cpu_helper.c
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@ -357,7 +357,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical,
* was called. Background registers will be used if the guest has
* forced a two stage translation to be on (in HS or M mode).
*/
if (!riscv_cpu_virt_enabled(env) && riscv_cpu_two_stage_lookup(mmu_idx)) {
if (!riscv_cpu_virt_enabled(env) && two_stage) {
use_background = true;
}